67 lines
1.8 KiB
LLVM
67 lines
1.8 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs | FileCheck %s
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; FIXME: We have implemented the following patterns in DAGCombiner.cpp,
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; but we can't get results as expected.
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; fold (or (and X, (xor Y, -1)), Y) to (or X, Y)
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define i32 @pattern1(i32 %x, i32 %y){
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; CHECK-LABEL: pattern1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xori 5, 4, 65535
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; CHECK-NEXT: xoris 5, 5, 65535
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; CHECK-NEXT: and 3, 3, 5
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: blr
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%a = xor i32 %y, -1
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%b = and i32 %x, %a
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%c = or i32 %b, %y
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ret i32 %c
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}
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; fold (or (and (xor Y, -1), X), Y) to (or X, Y)
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define i32 @pattern2(i32 %x, i32 %y){
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; CHECK-LABEL: pattern2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xori 5, 4, 65535
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; CHECK-NEXT: xoris 5, 5, 65535
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; CHECK-NEXT: and 3, 5, 3
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: blr
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%a = xor i32 %y, -1
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%b = and i32 %a, %x
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%c = or i32 %b, %y
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ret i32 %c
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}
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; fold (and (select Cond, 0, -1), X) to (select Cond, 0, X)
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define i32 @pattern3(i1 %cond, i32 %x) {
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; CHECK-LABEL: pattern3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li 5, -1
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; CHECK-NEXT: andi. 3, 3, 1
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; CHECK-NEXT: rldic 3, 5, 0, 32
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; CHECK-NEXT: iselgt 3, 0, 3
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; CHECK-NEXT: and 3, 3, 4
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; CHECK-NEXT: blr
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%sel = select i1 %cond, i32 0, i32 -1
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%res = and i32 %sel, %x
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ret i32 %res
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}
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; fold (or X, (select Cond, -1, 0)) to (select Cond, -1, X)
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define i32 @pattern4(i1 %cond, i32 %x) {
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; CHECK-LABEL: pattern4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li 5, -1
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; CHECK-NEXT: andi. 3, 3, 1
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; CHECK-NEXT: rldic 3, 5, 0, 32
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; CHECK-NEXT: li 5, 0
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; CHECK-NEXT: iselgt 3, 3, 5
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; CHECK-NEXT: or 3, 4, 3
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; CHECK-NEXT: blr
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%sel = select i1 %cond, i32 -1, i32 0
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%res = or i32 %x, %sel
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ret i32 %res
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}
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