43 lines
1.5 KiB
LLVM
43 lines
1.5 KiB
LLVM
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=SM20
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; RUN: llc < %s -march=nvptx -mcpu=sm_30 | FileCheck %s --check-prefix=SM30
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target triple = "nvptx-unknown-cuda"
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declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32)
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declare i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)*)
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; SM20-LABEL: .entry foo
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; SM30-LABEL: .entry foo
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define void @foo(i64 %img, i32 %val, i32 %idx) {
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; SM20: ld.param.u64 %rd[[SURFREG:[0-9]+]], [foo_param_0];
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; SM20: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
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; SM30: ld.param.u64 %rd[[SURFREG:[0-9]+]], [foo_param_0];
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; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
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tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %img, i32 %idx, i32 %val)
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ret void
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}
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@surf0 = internal addrspace(1) global i64 0, align 8
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; SM20-LABEL: .entry bar
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; SM30-LABEL: .entry bar
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define void @bar(i32 %val, i32 %idx) {
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; SM30: mov.u64 %rd[[SURFHANDLE:[0-9]+]], surf0
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%surfHandle = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @surf0)
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; SM20: sust.b.1d.b32.trap [surf0, {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
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; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
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tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %surfHandle, i32 %idx, i32 %val)
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ret void
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}
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!nvvm.annotations = !{!1, !2, !3}
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!1 = !{void (i64, i32, i32)* @foo, !"kernel", i32 1}
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!2 = !{void (i32, i32)* @bar, !"kernel", i32 1}
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!3 = !{i64 addrspace(1)* @surf0, !"surface", i32 1}
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