95 lines
3.7 KiB
LLVM
95 lines
3.7 KiB
LLVM
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_30 | FileCheck %s
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declare i32 @llvm.nvvm.shfl.sync.down.i32(i32, i32, i32, i32)
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declare float @llvm.nvvm.shfl.sync.down.f32(float, i32, i32, i32)
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declare i32 @llvm.nvvm.shfl.sync.up.i32(i32, i32, i32, i32)
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declare float @llvm.nvvm.shfl.sync.up.f32(float, i32, i32, i32)
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declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32)
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declare float @llvm.nvvm.shfl.sync.bfly.f32(float, i32, i32, i32)
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declare i32 @llvm.nvvm.shfl.sync.idx.i32(i32, i32, i32, i32)
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declare float @llvm.nvvm.shfl.sync.idx.f32(float, i32, i32, i32)
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; CHECK-LABEL: .func{{.*}}shfl.sync.rrr
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define i32 @shfl.sync.rrr(i32 %mask, i32 %a, i32 %b, i32 %c) {
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; CHECK: ld.param.u32 [[MASK:%r[0-9]+]]
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; CHECK: ld.param.u32 [[A:%r[0-9]+]]
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; CHECK: ld.param.u32 [[B:%r[0-9]+]]
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; CHECK: ld.param.u32 [[C:%r[0-9]+]]
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; CHECK: shfl.sync.down.b32 [[OUT:%r[0-9]+]], [[A]], [[B]], [[C]], [[MASK]];
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; CHECK: st.param.{{.}}32 {{.*}}, [[OUT]]
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%val = call i32 @llvm.nvvm.shfl.sync.down.i32(i32 %mask, i32 %a, i32 %b, i32 %c)
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ret i32 %val
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}
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; CHECK-LABEL: .func{{.*}}shfl.sync.irr
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define i32 @shfl.sync.irr(i32 %a, i32 %b, i32 %c) {
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; CHECK: ld.param.u32 [[A:%r[0-9]+]]
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; CHECK: ld.param.u32 [[B:%r[0-9]+]]
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; CHECK: ld.param.u32 [[C:%r[0-9]+]]
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; CHECK: shfl.sync.down.b32 [[OUT:%r[0-9]+]], [[A]], [[B]], [[C]], 1;
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; CHECK: st.param.{{.}}32 {{.*}}, [[OUT]]
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%val = call i32 @llvm.nvvm.shfl.sync.down.i32(i32 1, i32 %a, i32 %b, i32 %c)
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ret i32 %val
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}
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; CHECK-LABEL: .func{{.*}}shfl.sync.rri
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define i32 @shfl.sync.rri(i32 %mask, i32 %a, i32 %b) {
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; CHECK: ld.param.u32 [[MASK:%r[0-9]+]]
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; CHECK: ld.param.u32 [[A:%r[0-9]+]]
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; CHECK: ld.param.u32 [[B:%r[0-9]+]]
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; CHECK: shfl.sync.down.b32 [[OUT:%r[0-9]+]], [[A]], [[B]], 1, [[MASK]];
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; CHECK: st.param.{{.}}32 {{.*}}, [[OUT]]
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%val = call i32 @llvm.nvvm.shfl.sync.down.i32(i32 %mask, i32 %a, i32 %b, i32 1)
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ret i32 %val
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}
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; CHECK-LABEL: .func{{.*}}shfl.sync.iri
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define i32 @shfl.sync.iri(i32 %a, i32 %b) {
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; CHECK: ld.param.u32 [[A:%r[0-9]+]]
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; CHECK: ld.param.u32 [[B:%r[0-9]+]]
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; CHECK: shfl.sync.down.b32 [[OUT:%r[0-9]+]], [[A]], [[B]], 2, 1;
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; CHECK: st.param.{{.}}32 {{.*}}, [[OUT]]
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%val = call i32 @llvm.nvvm.shfl.sync.down.i32(i32 1, i32 %a, i32 %b, i32 2)
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ret i32 %val
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}
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; CHECK-LABEL: .func{{.*}}shfl.sync.rir
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define i32 @shfl.sync.rir(i32 %mask, i32 %a, i32 %c) {
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; CHECK: ld.param.u32 [[MASK:%r[0-9]+]]
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; CHECK: ld.param.u32 [[A:%r[0-9]+]]
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; CHECK: ld.param.u32 [[C:%r[0-9]+]]
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; CHECK: shfl.sync.down.b32 [[OUT:%r[0-9]+]], [[A]], 1, [[C]], [[MASK]];
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; CHECK: st.param.{{.}}32 {{.*}}, [[OUT]]
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%val = call i32 @llvm.nvvm.shfl.sync.down.i32(i32 %mask, i32 %a, i32 1, i32 %c)
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ret i32 %val
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}
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; CHECK-LABEL: .func{{.*}}shfl.sync.iir
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define i32 @shfl.sync.iir(i32 %a, i32 %c) {
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; CHECK: ld.param.u32 [[A:%r[0-9]+]]
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; CHECK: ld.param.u32 [[C:%r[0-9]+]]
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; CHECK: shfl.sync.down.b32 [[OUT:%r[0-9]+]], [[A]], 2, [[C]], 1;
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; CHECK: st.param.{{.}}32 {{.*}}, [[OUT]]
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%val = call i32 @llvm.nvvm.shfl.sync.down.i32(i32 1, i32 %a, i32 2, i32 %c)
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ret i32 %val
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}
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; CHECK-LABEL: .func{{.*}}shfl.sync.rii
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define i32 @shfl.sync.rii(i32 %mask, i32 %a) {
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; CHECK: ld.param.u32 [[MASK:%r[0-9]+]]
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; CHECK: ld.param.u32 [[A:%r[0-9]+]]
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; CHECK: shfl.sync.down.b32 [[OUT:%r[0-9]+]], [[A]], 1, 2, [[MASK]];
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; CHECK: st.param.{{.}}32 {{.*}}, [[OUT]]
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%val = call i32 @llvm.nvvm.shfl.sync.down.i32(i32 %mask, i32 %a, i32 1, i32 2)
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ret i32 %val
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}
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; CHECK-LABEL: .func{{.*}}shfl.sync.iii
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define i32 @shfl.sync.iii(i32 %a, i32 %b) {
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; CHECK: ld.param.u32 [[A:%r[0-9]+]]
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; CHECK: shfl.sync.down.b32 [[OUT:%r[0-9]+]], [[A]], 2, 3, 1;
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; CHECK: st.param.{{.}}32 {{.*}}, [[OUT]]
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%val = call i32 @llvm.nvvm.shfl.sync.down.i32(i32 1, i32 %a, i32 2, i32 3)
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ret i32 %val
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}
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