28 lines
1.1 KiB
LLVM
28 lines
1.1 KiB
LLVM
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; RUN: opt < %s -S -nvptx-lower-args | FileCheck %s --check-prefix IR
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; RUN: llc < %s -mcpu=sm_20 | FileCheck %s --check-prefix PTX
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target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"
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%class.outer = type <{ %class.inner, i32, [4 x i8] }>
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%class.inner = type { i32*, i32* }
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; Check that nvptx-lower-args preserves arg alignment
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define void @load_alignment(%class.outer* nocapture readonly byval(%class.outer) align 8 %arg) {
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entry:
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; IR: load %class.outer, %class.outer addrspace(101)*
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; IR-SAME: align 8
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; PTX: ld.param.u64
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; PTX-NOT: ld.param.u8
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%arg.idx = getelementptr %class.outer, %class.outer* %arg, i64 0, i32 0, i32 0
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%arg.idx.val = load i32*, i32** %arg.idx, align 8
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%arg.idx1 = getelementptr %class.outer, %class.outer* %arg, i64 0, i32 0, i32 1
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%arg.idx1.val = load i32*, i32** %arg.idx1, align 8
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%arg.idx2 = getelementptr %class.outer, %class.outer* %arg, i64 0, i32 1
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%arg.idx2.val = load i32, i32* %arg.idx2, align 8
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%arg.idx.val.val = load i32, i32* %arg.idx.val, align 4
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%add.i = add nsw i32 %arg.idx.val.val, %arg.idx2.val
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store i32 %add.i, i32* %arg.idx1.val, align 4
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ret void
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}
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