117 lines
5.3 KiB
LLVM
117 lines
5.3 KiB
LLVM
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; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s
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; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s
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; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32-INV %s
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; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32-INV %s
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; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
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; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
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; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,O32-INV %s
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; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,O32-INV %s
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; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
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; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
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; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N32-INV %s
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; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N32-INV %s
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; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
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; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
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; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s
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; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s
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; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -filetype=obj < %s -o - | llvm-objdump --no-show-raw-insn --arch=mips --mcpu=mips32r6 --mattr=micromips -d - | FileCheck --check-prefix=MM32R6 %s
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; Test the callee-saved registers are callee-saved as specified by section
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; 2 of the MIPSpro N32 Handbook and section 3 of the SYSV ABI spec.
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define void @fpu_clobber() nounwind {
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entry:
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call void asm "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f12},~{$f13},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
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ret void
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}
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; ALL-LABEL: fpu_clobber:
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; ALL-INV-NOT: sdc1 $f0,
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; ALL-INV-NOT: sdc1 $f1,
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; ALL-INV-NOT: sdc1 $f2,
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; ALL-INV-NOT: sdc1 $f3,
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; ALL-INV-NOT: sdc1 $f4,
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; ALL-INV-NOT: sdc1 $f5,
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; ALL-INV-NOT: sdc1 $f6,
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; ALL-INV-NOT: sdc1 $f7,
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; ALL-INV-NOT: sdc1 $f8,
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; ALL-INV-NOT: sdc1 $f9,
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; ALL-INV-NOT: sdc1 $f10,
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; ALL-INV-NOT: sdc1 $f11,
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; ALL-INV-NOT: sdc1 $f12,
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; ALL-INV-NOT: sdc1 $f13,
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; ALL-INV-NOT: sdc1 $f14,
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; ALL-INV-NOT: sdc1 $f15,
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; ALL-INV-NOT: sdc1 $f16,
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; ALL-INV-NOT: sdc1 $f17,
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; ALL-INV-NOT: sdc1 $f18,
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; ALL-INV-NOT: sdc1 $f19,
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; ALL-INV-NOT: sdc1 $f21,
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; ALL-INV-NOT: sdc1 $f23,
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; O32: addiu $sp, $sp, -48
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; O32-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)
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; O32-DAG: sdc1 [[F22:\$f22]], [[OFF22:[0-9]+]]($sp)
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; O32-DAG: sdc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp)
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; O32-DAG: sdc1 [[F26:\$f26]], [[OFF26:[0-9]+]]($sp)
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; O32-DAG: sdc1 [[F28:\$f28]], [[OFF28:[0-9]+]]($sp)
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; O32-DAG: sdc1 [[F30:\$f30]], [[OFF30:[0-9]+]]($sp)
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; O32-DAG: ldc1 [[F20]], [[OFF20]]($sp)
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; O32-DAG: ldc1 [[F22]], [[OFF22]]($sp)
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; O32-DAG: ldc1 [[F24]], [[OFF24]]($sp)
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; O32-INV-NOT: sdc1 $f25,
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; O32-DAG: ldc1 [[F26]], [[OFF26]]($sp)
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; O32-INV-NOT: sdc1 $f27,
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; O32-DAG: ldc1 [[F28]], [[OFF28]]($sp)
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; O32-INV-NOT: sdc1 $f29,
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; O32-DAG: ldc1 [[F30]], [[OFF30]]($sp)
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; O32-INV-NOT: sdc1 $f31,
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; O32: addiu $sp, $sp, 48
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; N32: addiu $sp, $sp, -48
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; N32-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)
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; N32-DAG: sdc1 [[F22:\$f22]], [[OFF22:[0-9]+]]($sp)
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; N32-DAG: sdc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp)
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; N32-DAG: sdc1 [[F26:\$f26]], [[OFF26:[0-9]+]]($sp)
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; N32-DAG: sdc1 [[F28:\$f28]], [[OFF28:[0-9]+]]($sp)
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; N32-DAG: sdc1 [[F30:\$f30]], [[OFF30:[0-9]+]]($sp)
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; N32-DAG: ldc1 [[F20]], [[OFF20]]($sp)
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; N32-DAG: ldc1 [[F22]], [[OFF22]]($sp)
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; N32-DAG: ldc1 [[F24]], [[OFF24]]($sp)
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; N32-INV-NOT: sdc1 $f25,
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; N32-DAG: ldc1 [[F26]], [[OFF26]]($sp)
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; N32-INV-NOT: sdc1 $f27,
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; N32-DAG: ldc1 [[F28]], [[OFF28]]($sp)
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; N32-INV-NOT: sdc1 $f29,
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; N32-DAG: ldc1 [[F30]], [[OFF30]]($sp)
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; N32-INV-NOT: sdc1 $f31,
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; N32: addiu $sp, $sp, 48
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; N64: addiu $sp, $sp, -64
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; N64-INV-NOT: sdc1 $f20,
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; N64-INV-NOT: sdc1 $f22,
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; N64-DAG: sdc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp)
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; N64-DAG: sdc1 [[F25:\$f25]], [[OFF25:[0-9]+]]($sp)
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; N64-DAG: sdc1 [[F26:\$f26]], [[OFF26:[0-9]+]]($sp)
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; N64-DAG: sdc1 [[F27:\$f27]], [[OFF27:[0-9]+]]($sp)
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; N64-DAG: sdc1 [[F28:\$f28]], [[OFF28:[0-9]+]]($sp)
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; N64-DAG: sdc1 [[F29:\$f29]], [[OFF29:[0-9]+]]($sp)
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; N64-DAG: sdc1 [[F30:\$f30]], [[OFF30:[0-9]+]]($sp)
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; N64-DAG: sdc1 [[F31:\$f31]], [[OFF31:[0-9]+]]($sp)
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; N64-DAG: ldc1 [[F24]], [[OFF24]]($sp)
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; N64-DAG: ldc1 [[F25]], [[OFF25]]($sp)
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; N64-DAG: ldc1 [[F26]], [[OFF26]]($sp)
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; N64-DAG: ldc1 [[F27]], [[OFF27]]($sp)
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; N64-DAG: ldc1 [[F28]], [[OFF28]]($sp)
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; N64-DAG: ldc1 [[F29]], [[OFF29]]($sp)
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; N64-DAG: ldc1 [[F30]], [[OFF30]]($sp)
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; N64-DAG: ldc1 [[F31]], [[OFF31]]($sp)
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; N64: addiu $sp, $sp, 64
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; Check the mapping between LDC164 and LDC1_64_MMR6.
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; MM32R6: ldc1
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