llvm-for-llvmta/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir

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2022-04-25 10:02:23 +02:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define i32 @Unconditional_branch(i32 %a, i32 %b) {
entry:
br label %block
end: ; preds = %block
ret i32 %a
block: ; preds = %entry
br label %end
}
define i32 @Conditional_branch(i1 %cond, i32 %a, i32 %b) {
br i1 %cond, label %if.then, label %if.else
if.then: ; preds = %0
ret i32 %a
if.else: ; preds = %0
ret i32 %b
}
...
---
name: Unconditional_branch
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
; MIPS32-LABEL: name: Unconditional_branch
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.2(0x80000000)
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.end:
; MIPS32: $v0 = COPY [[COPY]](s32)
; MIPS32: RetRA implicit $v0
; MIPS32: bb.2.block:
; MIPS32: successors: %bb.1(0x80000000)
; MIPS32: G_BR %bb.1
bb.1.entry:
liveins: $a0, $a1
%0:_(s32) = COPY $a0
G_BR %bb.3
bb.2.end:
$v0 = COPY %0(s32)
RetRA implicit $v0
bb.3.block:
G_BR %bb.2
...
---
name: Conditional_branch
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
; MIPS32-LABEL: name: Conditional_branch
; MIPS32: bb.0 (%ir-block.0):
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; MIPS32: liveins: $a0, $a1, $a2
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.if.then:
; MIPS32: $v0 = COPY [[COPY1]](s32)
; MIPS32: RetRA implicit $v0
; MIPS32: bb.2.if.else:
; MIPS32: $v0 = COPY [[COPY2]](s32)
; MIPS32: RetRA implicit $v0
bb.1 (%ir-block.0):
liveins: $a0, $a1, $a2
%3:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = COPY $a2
%5:_(s32) = G_CONSTANT i32 1
%6:_(s32) = COPY %3(s32)
%4:_(s32) = G_AND %6, %5
G_BRCOND %4(s32), %bb.2
G_BR %bb.3
bb.2.if.then:
$v0 = COPY %1(s32)
RetRA implicit $v0
bb.3.if.else:
$v0 = COPY %2(s32)
RetRA implicit $v0
...