40 lines
1.6 KiB
Plaintext
40 lines
1.6 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
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# Check there are no COPY instructions surrounding ADDVI_W instruction.
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# MIParser sets RegClassOrRegBank for parsed virtual registers.
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# Constraining register classes when G_INTRINSIC intrinsic(@llvm.mips.addvi.w)
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# gets selected into ADDVI_W works as expected.
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# Check that setRegClassOrRegBank.ll has same output.
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--- |
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declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)
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define void @add_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) { entry: ret void }
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...
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---
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name: add_v4i32_builtin_imm
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; P5600-LABEL: name: add_v4i32_builtin_imm
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; P5600: liveins: $a0, $a1
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; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
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; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
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; P5600: [[ADDVI_W:%[0-9]+]]:msa128w(<4 x s32>) = ADDVI_W [[LOAD]](<4 x s32>), 25
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; P5600: G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
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; P5600: RetRA
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%0:_(p0) = COPY $a0
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%1:_(p0) = COPY $a1
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%2:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
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%3:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.w), %2(<4 x s32>), 25
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G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.c)
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RetRA
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...
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