19 lines
620 B
LLVM
19 lines
620 B
LLVM
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Make sure that element no.1 extracted from <2 x i1> translates to extracting
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; bit no.4 from the predicate register.
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; CHECK: p[[P0:[0-3]]] = vcmpw.eq(r1:0,r3:2)
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; CHECK: r[[R0:[0-9]+]] = p[[P0]]
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; This is what we're really testing: the bit index of 4.
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; CHECK: p[[P0]] = tstbit(r[[R0]],#4)
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define i32 @fred(<2 x i32> %a0, <2 x i32> %a1) #0 {
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%v0 = icmp eq <2 x i32> %a0, %a1
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%v1 = extractelement <2 x i1> %v0, i32 1
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%v2 = zext i1 %v1 to i32
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ret i32 %v2
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}
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attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
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