136 lines
3.8 KiB
LLVM
136 lines
3.8 KiB
LLVM
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s
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; Hexagon Programmer's Reference Manual 11.2 CR
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; CHECK-CALL-NOT: call
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; Corner detection acceleration
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declare i32 @llvm.hexagon.C4.fastcorner9(i32, i32)
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define i32 @C4_fastcorner9(i32 %a, i32 %b) {
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%z = call i32@llvm.hexagon.C4.fastcorner9(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = fastcorner9({{.*}},{{.*}})
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declare i32 @llvm.hexagon.C4.fastcorner9.not(i32, i32)
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define i32 @C4_fastcorner9_not(i32 %a, i32 %b) {
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%z = call i32@llvm.hexagon.C4.fastcorner9.not(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = !fastcorner9({{.*}},{{.*}})
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; Logical reductions on predicates
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declare i32 @llvm.hexagon.C2.any8(i32)
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define i32 @C2_any8(i32 %a) {
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%z = call i32@llvm.hexagon.C2.any8(i32 %a)
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ret i32 %z
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}
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; CHECK: = any8({{.*}})
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declare i32 @llvm.hexagon.C2.all8(i32)
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define i32 @C2_all8(i32 %a) {
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%z = call i32@llvm.hexagon.C2.all8(i32 %a)
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ret i32 %z
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}
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; CHECK: = all8({{.*}})
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; Logical operations on predicates
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declare i32 @llvm.hexagon.C2.and(i32, i32)
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define i32 @C2_and(i32 %a, i32 %b) {
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%z = call i32@llvm.hexagon.C2.and(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = and({{.*}},{{.*}})
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declare i32 @llvm.hexagon.C4.and.and(i32, i32, i32)
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define i32 @C4_and_and(i32 %a, i32 %b, i32 %c) {
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%z = call i32@llvm.hexagon.C4.and.and(i32 %a, i32 %b, i32 %c)
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ret i32 %z
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}
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; CHECK: = and({{.*}},and({{.*}},{{.*}}))
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declare i32 @llvm.hexagon.C2.or(i32, i32)
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define i32 @C2_or(i32 %a, i32 %b) {
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%z = call i32@llvm.hexagon.C2.or(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = or({{.*}},{{.*}})
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declare i32 @llvm.hexagon.C4.and.or(i32, i32, i32)
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define i32 @C4_and_or(i32 %a, i32 %b, i32 %c) {
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%z = call i32@llvm.hexagon.C4.and.or(i32 %a, i32 %b, i32 %c)
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ret i32 %z
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}
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; CHECK: = and({{.*}},or({{.*}},{{.*}}))
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declare i32 @llvm.hexagon.C2.xor(i32, i32)
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define i32 @C2_xor(i32 %a, i32 %b) {
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%z = call i32@llvm.hexagon.C2.xor(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = xor({{.*}},{{.*}})
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declare i32 @llvm.hexagon.C4.or.and(i32, i32, i32)
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define i32 @C4_or_and(i32 %a, i32 %b, i32 %c) {
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%z = call i32@llvm.hexagon.C4.or.and(i32 %a, i32 %b, i32 %c)
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ret i32 %z
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}
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; CHECK: = or({{.*}},and({{.*}},{{.*}}))
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declare i32 @llvm.hexagon.C2.andn(i32, i32)
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define i32 @C2_andn(i32 %a, i32 %b) {
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%z = call i32@llvm.hexagon.C2.andn(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = and({{.*}},!{{.*}})
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declare i32 @llvm.hexagon.C4.or.or(i32, i32, i32)
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define i32 @C4_or_or(i32 %a, i32 %b, i32 %c) {
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%z = call i32@llvm.hexagon.C4.or.or(i32 %a, i32 %b, i32 %c)
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ret i32 %z
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}
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; CHECK: = or({{.*}},or({{.*}},{{.*}}))
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declare i32 @llvm.hexagon.C4.and.andn(i32, i32, i32)
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define i32 @C4_and_andn(i32 %a, i32 %b, i32 %c) {
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%z = call i32@llvm.hexagon.C4.and.andn(i32 %a, i32 %b, i32 %c)
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ret i32 %z
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}
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; CHECK: = and({{.*}},and({{.*}},!{{.*}}))
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declare i32 @llvm.hexagon.C4.and.orn(i32, i32, i32)
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define i32 @C4_and_orn(i32 %a, i32 %b, i32 %c) {
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%z = call i32@llvm.hexagon.C4.and.orn(i32 %a, i32 %b, i32 %c)
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ret i32 %z
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}
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; CHECK: = and({{.*}},or({{.*}},!{{.*}}))
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declare i32 @llvm.hexagon.C2.not(i32)
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define i32 @C2_not(i32 %a) {
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%z = call i32@llvm.hexagon.C2.not(i32 %a)
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ret i32 %z
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}
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; CHECK: = not({{.*}})
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declare i32 @llvm.hexagon.C4.or.andn(i32, i32, i32)
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define i32 @C4_or_andn(i32 %a, i32 %b, i32 %c) {
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%z = call i32@llvm.hexagon.C4.or.andn(i32 %a, i32 %b, i32 %c)
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ret i32 %z
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}
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; CHECK: = or({{.*}},and({{.*}},!{{.*}}))
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declare i32 @llvm.hexagon.C2.orn(i32, i32)
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define i32 @C2_orn(i32 %a, i32 %b) {
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%z = call i32@llvm.hexagon.C2.orn(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = or({{.*}},!{{.*}})
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declare i32 @llvm.hexagon.C4.or.orn(i32, i32, i32)
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define i32 @C4_or_orn(i32 %a, i32 %b, i32 %c) {
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%z = call i32@llvm.hexagon.C4.or.orn(i32 %a, i32 %b, i32 %c)
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ret i32 %z
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}
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; CHECK: = or({{.*}},or({{.*}},!{{.*}}))
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