112 lines
5.0 KiB
LLVM
112 lines
5.0 KiB
LLVM
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; RUN: llc -march=amdgcn -disable-promote-alloca-to-vector -verify-machineinstrs < %s | FileCheck %s
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declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #1
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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; CI+ intrinsic
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declare void @llvm.amdgcn.s.dcache.inv.vol() #0
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; VI+ intrinsic
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declare void @llvm.amdgcn.s.dcache.wb() #0
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; CHECK-LABEL: {{^}}target_none:
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; CHECK: s_movk_i32 [[OFFSETREG:s[0-9]+]], 0x400
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; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, [[OFFSETREG]]
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; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
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define amdgpu_kernel void @target_none() #0 {
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%kernargs = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
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%kernargs.gep = getelementptr inbounds i8, i8 addrspace(4)* %kernargs, i64 1024
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%kernargs.gep.cast = bitcast i8 addrspace(4)* %kernargs.gep to i32 addrspace(1)* addrspace(4)*
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%ptr = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* %kernargs.gep.cast
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%id.ext = sext i32 %id to i64
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %ptr, i64 %id.ext
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store i32 0, i32 addrspace(1)* %gep
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ret void
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}
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; CHECK-LABEL: {{^}}target_tahiti:
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; CHECK: s_movk_i32 [[OFFSETREG:s[0-9]+]], 0x400
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; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, [[OFFSETREG]]
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; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
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define amdgpu_kernel void @target_tahiti() #1 {
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%kernargs = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
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%kernargs.gep = getelementptr inbounds i8, i8 addrspace(4)* %kernargs, i64 1024
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%kernargs.gep.cast = bitcast i8 addrspace(4)* %kernargs.gep to i32 addrspace(1)* addrspace(4)*
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%ptr = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* %kernargs.gep.cast
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%id.ext = sext i32 %id to i64
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %ptr, i64 %id.ext
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store i32 0, i32 addrspace(1)* %gep
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ret void
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}
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; CHECK-LABEL: {{^}}target_bonaire:
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; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x100
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; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
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; CHECK: s_dcache_inv_vol
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define amdgpu_kernel void @target_bonaire() #3 {
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%kernargs = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
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%kernargs.gep = getelementptr inbounds i8, i8 addrspace(4)* %kernargs, i64 1024
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%kernargs.gep.cast = bitcast i8 addrspace(4)* %kernargs.gep to i32 addrspace(1)* addrspace(4)*
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%ptr = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* %kernargs.gep.cast
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%id.ext = sext i32 %id to i64
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %ptr, i64 %id.ext
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store i32 0, i32 addrspace(1)* %gep
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call void @llvm.amdgcn.s.dcache.inv.vol()
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ret void
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}
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; CHECK-LABEL: {{^}}target_fiji:
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; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x400
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; CHECK: flat_store_dword
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; CHECK: s_dcache_wb{{$}}
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define amdgpu_kernel void @target_fiji() #4 {
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%kernargs = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
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%kernargs.gep = getelementptr inbounds i8, i8 addrspace(4)* %kernargs, i64 1024
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%kernargs.gep.cast = bitcast i8 addrspace(4)* %kernargs.gep to i32 addrspace(1)* addrspace(4)*
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%ptr = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* %kernargs.gep.cast
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%id.ext = sext i32 %id to i64
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %ptr, i64 %id.ext
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store i32 0, i32 addrspace(1)* %gep
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call void @llvm.amdgcn.s.dcache.wb()
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ret void
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}
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; CHECK-LABEL: {{^}}promote_alloca_enabled:
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; CHECK: ds_read_b32
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define amdgpu_kernel void @promote_alloca_enabled(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #5 {
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entry:
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%stack = alloca [5 x i32], align 4, addrspace(5)
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%tmp = load i32, i32 addrspace(1)* %in, align 4
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%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp
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%load = load i32, i32 addrspace(5)* %arrayidx1
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store i32 %load, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}promote_alloca_disabled:
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; CHECK: SCRATCH_RSRC_DWORD0
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; CHECK: SCRATCH_RSRC_DWORD1
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; CHECK: ScratchSize: 24
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define amdgpu_kernel void @promote_alloca_disabled(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #6 {
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entry:
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%stack = alloca [5 x i32], align 4, addrspace(5)
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%tmp = load i32, i32 addrspace(1)* %in, align 4
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%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp
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%load = load i32, i32 addrspace(5)* %arrayidx1
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store i32 %load, i32 addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind "target-cpu"="tahiti" }
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attributes #3 = { nounwind "target-cpu"="bonaire" }
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attributes #4 = { nounwind "target-cpu"="fiji" }
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attributes #5 = { nounwind "target-features"="+promote-alloca" "amdgpu-waves-per-eu"="1,3" }
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attributes #6 = { nounwind "target-features"="-promote-alloca" "amdgpu-waves-per-eu"="1,3" }
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