69 lines
2.6 KiB
Plaintext
69 lines
2.6 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -run-pass=regbankselect %s -o - | FileCheck -check-prefix=SI %s
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--- |
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define amdgpu_ps i96 @split_smrd_load_range(i96 addrspace(4)* %ptr) {
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%load = load i96, i96 addrspace(4)* %ptr, !range !0
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ret i96 %load
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}
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define amdgpu_ps <3 x i32> @split_smrd_load_tbaa(<3 x i32> addrspace(4)* %ptr) {
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%load = load <3 x i32>, <3 x i32> addrspace(4)* %ptr, !tbaa !1
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ret <3 x i32> %load
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}
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!0 = !{i96 0, i96 9223372036854775808}
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!1 = !{!"omnipotent char", !2}
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!2 = !{!"Simple C/C++ TBAA"}
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...
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# Make sure range metadata is not preserved when widening loads, but
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# tbaa is.
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---
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name: split_smrd_load_range
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; SI-LABEL: name: split_smrd_load_range
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; SI: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
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; SI: [[LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_LOAD [[COPY]](p4) :: (load 8, addrspace 4)
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; SI: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 8
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; SI: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
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; SI: [[LOAD1:%[0-9]+]]:sgpr(s32) = G_LOAD [[PTR_ADD]](p4) :: (load 4 + 8, align 8, addrspace 4)
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; SI: [[DEF:%[0-9]+]]:sgpr(<3 x s32>) = G_IMPLICIT_DEF
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; SI: [[INSERT:%[0-9]+]]:sgpr(<3 x s32>) = G_INSERT [[DEF]], [[LOAD]](<2 x s32>), 0
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; SI: [[INSERT1:%[0-9]+]]:sgpr(<3 x s32>) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64
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; SI: $sgpr0_sgpr1_sgpr2 = COPY [[INSERT1]](<3 x s32>)
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%0:_(p4) = COPY $sgpr0_sgpr1
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%1:_(<3 x s32>) = G_LOAD %0 :: (load 12, align 8, addrspace 4, !range !0)
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$sgpr0_sgpr1_sgpr2 = COPY %1
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...
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---
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name: split_smrd_load_tbaa
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; SI-LABEL: name: split_smrd_load_tbaa
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; SI: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
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; SI: [[LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_LOAD [[COPY]](p4) :: (load 8, !tbaa !2, addrspace 4)
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; SI: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 8
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; SI: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
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; SI: [[LOAD1:%[0-9]+]]:sgpr(s32) = G_LOAD [[PTR_ADD]](p4) :: (load 4 + 8, align 8, !tbaa !2, addrspace 4)
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; SI: [[DEF:%[0-9]+]]:sgpr(<3 x s32>) = G_IMPLICIT_DEF
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; SI: [[INSERT:%[0-9]+]]:sgpr(<3 x s32>) = G_INSERT [[DEF]], [[LOAD]](<2 x s32>), 0
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; SI: [[INSERT1:%[0-9]+]]:sgpr(<3 x s32>) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64
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; SI: $sgpr0_sgpr1_sgpr2 = COPY [[INSERT1]](<3 x s32>)
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%0:_(p4) = COPY $sgpr0_sgpr1
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%1:_(<3 x s32>) = G_LOAD %0 :: (load 12, align 8, addrspace 4, !tbaa !1)
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$sgpr0_sgpr1_sgpr2 = COPY %1
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...
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