40 lines
1.5 KiB
Plaintext
40 lines
1.5 KiB
Plaintext
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||
|
|
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
|
||
|
|
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
|
||
|
|
|
||
|
|
---
|
||
|
|
name: interp_mov_ss
|
||
|
|
legalized: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0, $sgpr1
|
||
|
|
; CHECK-LABEL: name: interp_mov_ss
|
||
|
|
; CHECK: liveins: $sgpr0, $sgpr1
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||
|
|
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||
|
|
; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.mov), [[COPY2]](s32), 1, 1, [[COPY1]](s32)
|
||
|
|
%0:_(s32) = COPY $sgpr0
|
||
|
|
%1:_(s32) = COPY $sgpr1
|
||
|
|
%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.mov), %0, 1, 1, %1
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: interp_mov_sv
|
||
|
|
legalized: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0, $vgpr0
|
||
|
|
; CHECK-LABEL: name: interp_mov_sv
|
||
|
|
; CHECK: liveins: $sgpr0, $vgpr0
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
|
||
|
|
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY]](s32), implicit $exec
|
||
|
|
; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.mov), 0, 1, 1, [[V_READFIRSTLANE_B32_]](s32)
|
||
|
|
%0:_(s32) = COPY $vgpr0
|
||
|
|
%1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.mov), 0, 1, 1, %0
|
||
|
|
...
|