83 lines
3.3 KiB
LLVM
83 lines
3.3 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -global-isel -march=amdgcn -mcpu=hawaii -stop-after=instruction-select -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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define amdgpu_ps float @wwm_f32(float %val) {
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; GCN-LABEL: name: wwm_f32
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; GCN: bb.1 (%ir-block.0):
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; GCN: liveins: $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[WWM:%[0-9]+]]:vgpr_32 = WWM [[COPY]], implicit $exec
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; GCN: $vgpr0 = COPY [[WWM]]
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; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0
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%ret = call float @llvm.amdgcn.wwm.f32(float %val)
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ret float %ret
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}
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define amdgpu_ps float @wwm_v2f16(float %arg) {
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; GCN-LABEL: name: wwm_v2f16
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; GCN: bb.1 (%ir-block.0):
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; GCN: liveins: $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[WWM:%[0-9]+]]:vgpr_32 = WWM [[COPY]], implicit $exec
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; GCN: $vgpr0 = COPY [[WWM]]
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; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0
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%val = bitcast float %arg to <2 x half>
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%ret = call <2 x half> @llvm.amdgcn.wwm.v2f16(<2 x half> %val)
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%bc = bitcast <2 x half> %ret to float
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ret float %bc
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}
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define amdgpu_ps <2 x float> @wwm_f64(double %val) {
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; GCN-LABEL: name: wwm_f64
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; GCN: bb.1 (%ir-block.0):
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; GCN: liveins: $vgpr0, $vgpr1
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
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; GCN: [[WWM:%[0-9]+]]:vreg_64 = WWM [[REG_SEQUENCE]], implicit $exec
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[WWM]].sub0
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; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[WWM]].sub1
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; GCN: $vgpr0 = COPY [[COPY2]]
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; GCN: $vgpr1 = COPY [[COPY3]]
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; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
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%ret = call double @llvm.amdgcn.wwm.f64(double %val)
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%bitcast = bitcast double %ret to <2 x float>
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ret <2 x float> %bitcast
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}
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; TODO
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; define amdgpu_ps float @wwm_i1_vcc(float %val) {
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; %vcc = fcmp oeq float %val, 0.0
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; %ret = call i1 @llvm.amdgcn.wwm.i1(i1 %vcc)
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; %select = select i1 %ret, float 1.0, float 0.0
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; ret float %select
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; }
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define amdgpu_ps <3 x float> @wwm_v3f32(<3 x float> %val) {
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; GCN-LABEL: name: wwm_v3f32
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; GCN: bb.1 (%ir-block.0):
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; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2
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; GCN: [[WWM:%[0-9]+]]:vreg_96 = WWM [[REG_SEQUENCE]], implicit $exec
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; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[WWM]].sub0
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; GCN: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[WWM]].sub1
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; GCN: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[WWM]].sub2
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; GCN: $vgpr0 = COPY [[COPY3]]
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; GCN: $vgpr1 = COPY [[COPY4]]
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; GCN: $vgpr2 = COPY [[COPY5]]
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; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
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%ret = call <3 x float> @llvm.amdgcn.wwm.v3f32(<3 x float> %val)
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ret <3 x float> %ret
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}
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declare i1 @llvm.amdgcn.wwm.i1(i1) #0
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declare float @llvm.amdgcn.wwm.f32(float) #0
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declare <2 x half> @llvm.amdgcn.wwm.v2f16(<2 x half>) #0
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declare <3 x float> @llvm.amdgcn.wwm.v3f32(<3 x float>) #0
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declare double @llvm.amdgcn.wwm.f64(double) #0
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attributes #0 = { nounwind readnone speculatable }
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