105 lines
3.3 KiB
Plaintext
105 lines
3.3 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s
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--- |
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define i32 @widen_load_range0_tbaa(i24 addrspace(1)* %ptr) {
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%load = load i24, i24 addrspace(1)* %ptr, !range !0, !tbaa !1
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%zext = zext i24 %load to i32
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ret i32 %zext
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}
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define i32 @widen_load_range1_tbaa(i24 addrspace(1)* %ptr) {
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%load = load i24, i24 addrspace(1)* %ptr, !range !0, !tbaa !1
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%zext = zext i24 %load to i32
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ret i32 %zext
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}
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define i32 @widen_load_tbaa0(i24 addrspace(1)* %ptr) {
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%load = load i24, i24 addrspace(1)* %ptr, !tbaa !1
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%zext = zext i24 %load to i32
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ret i32 %zext
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}
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define i32 @widen_load_tbaa1(i24 addrspace(1)* %ptr) {
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%load = load i24, i24 addrspace(1)* %ptr, !tbaa !1
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%zext = zext i24 %load to i32
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ret i32 %zext
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}
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!0 = !{i24 0, i24 1048575}
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!1 = !{!"omnipotent char", !2}
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!2 = !{!"Simple C/C++ TBAA"}
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...
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# Make sure range metadata is not preserved when widening loads, but
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# tbaa is.
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---
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name: widen_load_range0_tbaa
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; SI-LABEL: name: widen_load_range0_tbaa
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; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, !tbaa !1, addrspace 1)
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; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
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; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
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; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; SI: $vgpr0 = COPY [[AND]](s32)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(s24) = G_LOAD %0 :: (load 3, align 4, addrspace 1, !range !0, !tbaa !1)
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%2:_(s32) = G_ZEXT %1
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$vgpr0 = COPY %2
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...
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# Result register type already matches the widened memory type.
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---
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name: widen_load_range1_tbaa
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; SI-LABEL: name: widen_load_range1_tbaa
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; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, !tbaa !1, addrspace 1)
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; SI: $vgpr0 = COPY [[LOAD]](s32)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_LOAD %0 :: (load 3, align 4, addrspace 1, !range !0, !tbaa !1)
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$vgpr0 = COPY %1
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...
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---
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name: widen_load_tbaa0
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; SI-LABEL: name: widen_load_tbaa0
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; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, !tbaa !1, addrspace 1)
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; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
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; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
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; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; SI: $vgpr0 = COPY [[AND]](s32)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(s24) = G_LOAD %0 :: (load 3, align 4, addrspace 1, !tbaa !1)
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%2:_(s32) = G_ZEXT %1
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$vgpr0 = COPY %2
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...
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# Result register type already matches the widened memory type.
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---
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name: widen_load_tbaa1
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; SI-LABEL: name: widen_load_tbaa1
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; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, !tbaa !1, addrspace 1)
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; SI: $vgpr0 = COPY [[LOAD]](s32)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_LOAD %0 :: (load 3, align 4, addrspace 1, !tbaa !1)
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$vgpr0 = COPY %1
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...
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