137 lines
3.9 KiB
Plaintext
137 lines
3.9 KiB
Plaintext
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel*' -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERR %s
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# Make sure incorrect usage of control flow intrinsics fails to select in case some transform separated the intrinsic from its branch.
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# ERR: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_different_block)
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# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: si_if_not_brcond_user)
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# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: si_if_multi_user)
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# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_xor_0)
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# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_or_neg1)
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# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_negated_multi_use)
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---
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name: brcond_si_if_different_block
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body: |
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bb.0:
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successors: %bb.1
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liveins: $vgpr0, $vgpr1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s1) = G_ICMP intpred(ne), %0, %1
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%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
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bb.1:
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G_BRCOND %3, %bb.1
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...
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---
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name: si_if_not_brcond_user
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s1) = G_ICMP intpred(ne), %0, %1
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%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
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%5:_(s32) = G_SELECT %3, %0, %1
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S_ENDPGM 0, implicit %5
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...
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---
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name: si_if_multi_user
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s1) = G_ICMP intpred(ne), %0, %1
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%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
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%5:_(s32) = G_SELECT %3, %0, %1
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G_BRCOND %3, %bb.1
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bb.1:
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S_ENDPGM 0, implicit %5
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...
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# Make sure we only match G_XOR (if), -1
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---
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name: brcond_si_if_xor_0
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body: |
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bb.0:
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successors: %bb.1
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liveins: $vgpr0, $vgpr1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s1) = G_ICMP intpred(ne), %0, %1
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%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
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%5:_(s1) = G_CONSTANT i1 false
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%6:_(s1) = G_XOR %3, %5
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G_BRCOND %6, %bb.2
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G_BR %bb.3
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bb.1:
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S_NOP 0
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bb.2:
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S_NOP 1
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bb.3:
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S_NOP 2
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...
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# Make sure we only match G_XOR (if), -1
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---
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name: brcond_si_if_or_neg1
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body: |
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bb.0:
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successors: %bb.1
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liveins: $vgpr0, $vgpr1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s1) = G_ICMP intpred(ne), %0, %1
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%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
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%5:_(s1) = G_CONSTANT i1 true
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%6:_(s1) = G_OR %3, %5
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G_BRCOND %6, %bb.2
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G_BR %bb.3
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bb.1:
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S_NOP 0
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bb.2:
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S_NOP 1
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bb.3:
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S_NOP 2
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...
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---
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name: brcond_si_if_negated_multi_use
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body: |
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bb.0:
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successors: %bb.1
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liveins: $vgpr0, $vgpr1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s1) = G_ICMP intpred(ne), %0, %1
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%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
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%5:_(s1) = G_CONSTANT i1 true
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%6:_(s1) = G_XOR %3, %5
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S_NOP 0, implicit %6
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G_BRCOND %6, %bb.2
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G_BR %bb.3
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bb.1:
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S_NOP 0
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bb.2:
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S_NOP 1
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bb.3:
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S_NOP 2
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...
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