218 lines
5.3 KiB
Plaintext
218 lines
5.3 KiB
Plaintext
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||
|
|
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
|
||
|
|
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: anyext_sgpr_s16_to_sgpr_s32
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0
|
||
|
|
|
||
|
|
; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s32
|
||
|
|
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||
|
|
; GCN: $sgpr0 = COPY [[COPY]]
|
||
|
|
%0:sgpr(s32) = COPY $sgpr0
|
||
|
|
%1:sgpr(s16) = G_TRUNC %0
|
||
|
|
%2:sgpr(s32) = G_ANYEXT %1
|
||
|
|
$sgpr0 = COPY %2
|
||
|
|
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: anyext_sgpr_s32_to_sgpr_s64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0
|
||
|
|
|
||
|
|
; GCN-LABEL: name: anyext_sgpr_s32_to_sgpr_s64
|
||
|
|
; GCN: liveins: $sgpr0
|
||
|
|
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||
|
|
; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
|
||
|
|
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
|
||
|
|
; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
|
||
|
|
%0:sgpr(s32) = COPY $sgpr0
|
||
|
|
%1:sgpr(s64) = G_ANYEXT %0
|
||
|
|
S_ENDPGM 0, implicit %1
|
||
|
|
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: anyext_sgpr_s16_to_sgpr_s64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0
|
||
|
|
|
||
|
|
; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s64
|
||
|
|
; GCN: liveins: $sgpr0
|
||
|
|
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||
|
|
; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
|
||
|
|
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
|
||
|
|
; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
|
||
|
|
%0:sgpr(s32) = COPY $sgpr0
|
||
|
|
%1:sgpr(s16) = G_TRUNC %0
|
||
|
|
%2:sgpr(s64) = G_ANYEXT %1
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: anyext_vgpr_s32_to_vgpr_s64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0
|
||
|
|
|
||
|
|
; GCN-LABEL: name: anyext_vgpr_s32_to_vgpr_s64
|
||
|
|
; GCN: liveins: $vgpr0
|
||
|
|
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||
|
|
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||
|
|
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
|
||
|
|
; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
|
||
|
|
%0:vgpr(s32) = COPY $vgpr0
|
||
|
|
%1:vgpr(s64) = G_ANYEXT %0
|
||
|
|
S_ENDPGM 0, implicit %1
|
||
|
|
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: anyext_vgpr_s16_to_vgpr_s64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0
|
||
|
|
|
||
|
|
; GCN-LABEL: name: anyext_vgpr_s16_to_vgpr_s64
|
||
|
|
; GCN: liveins: $vgpr0
|
||
|
|
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||
|
|
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||
|
|
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
|
||
|
|
; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
|
||
|
|
%0:vgpr(s32) = COPY $vgpr0
|
||
|
|
%1:vgpr(s16) = G_TRUNC %0
|
||
|
|
%2:vgpr(s64) = G_ANYEXT %1
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
|
||
|
|
...
|
||
|
|
|
||
|
|
# vcc is an invalid extension source
|
||
|
|
# ---
|
||
|
|
|
||
|
|
# name: anyext_vcc_s1_to_vgpr_s32
|
||
|
|
# legalized: true
|
||
|
|
# regBankSelected: true
|
||
|
|
# body: |
|
||
|
|
# bb.0:
|
||
|
|
# liveins: $vgpr0
|
||
|
|
|
||
|
|
# %0:vgpr(s32) = COPY $vgpr0
|
||
|
|
# %1:vcc(s1) = G_ICMP intpred(eq), %0, %0
|
||
|
|
# %2:vgpr(s32) = G_ANYEXT %1
|
||
|
|
# $vgpr0 = COPY %2
|
||
|
|
# ...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: anyext_sgpr_s1_to_sgpr_s32
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0
|
||
|
|
|
||
|
|
; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s32
|
||
|
|
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||
|
|
; GCN: $sgpr0 = COPY [[COPY]]
|
||
|
|
%0:sgpr(s32) = COPY $sgpr0
|
||
|
|
%1:sgpr(s1) = G_TRUNC %0
|
||
|
|
%2:sgpr(s32) = G_ANYEXT %1
|
||
|
|
$sgpr0 = COPY %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: anyext_vgpr_s1_to_vgpr_s32
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0
|
||
|
|
|
||
|
|
; GCN-LABEL: name: anyext_vgpr_s1_to_vgpr_s32
|
||
|
|
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||
|
|
; GCN: $vgpr0 = COPY [[COPY]]
|
||
|
|
%0:vgpr(s32) = COPY $vgpr0
|
||
|
|
%1:vgpr(s1) = G_TRUNC %0
|
||
|
|
%2:vgpr(s32) = G_ANYEXT %1
|
||
|
|
$vgpr0 = COPY %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: anyext_sgpr_s1_to_vgpr_s32
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0
|
||
|
|
|
||
|
|
; GCN-LABEL: name: anyext_sgpr_s1_to_vgpr_s32
|
||
|
|
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||
|
|
; GCN: $sgpr0 = COPY [[COPY]]
|
||
|
|
%0:sgpr(s32) = COPY $sgpr0
|
||
|
|
%1:sgpr(s1) = G_TRUNC %0
|
||
|
|
%2:sgpr(s32) = G_ANYEXT %1
|
||
|
|
$sgpr0 = COPY %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: anyext_vgpr_s16_to_vgpr_s32
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0
|
||
|
|
|
||
|
|
; GCN-LABEL: name: anyext_vgpr_s16_to_vgpr_s32
|
||
|
|
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||
|
|
; GCN: $vgpr0 = COPY [[COPY]]
|
||
|
|
%0:vgpr(s32) = COPY $vgpr0
|
||
|
|
%1:vgpr(s16) = G_TRUNC %0
|
||
|
|
%2:vgpr(s32) = G_ANYEXT %1
|
||
|
|
$vgpr0 = COPY %2
|
||
|
|
|
||
|
|
...
|
||
|
|
|
||
|
|
# The source register already has an assigned register class that
|
||
|
|
# should not be interpreted as vcc.
|
||
|
|
---
|
||
|
|
|
||
|
|
name: anyext_regclass_sgpr_s1_to_sgpr_s32
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0
|
||
|
|
|
||
|
|
; GCN-LABEL: name: anyext_regclass_sgpr_s1_to_sgpr_s32
|
||
|
|
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||
|
|
; GCN: $sgpr0 = COPY [[COPY]]
|
||
|
|
%0:sgpr(s32) = COPY $sgpr0
|
||
|
|
%1:sreg_32(s1) = G_TRUNC %0
|
||
|
|
%2:sgpr(s32) = G_ANYEXT %1
|
||
|
|
$sgpr0 = COPY %2
|
||
|
|
...
|