522 lines
21 KiB
Plaintext
522 lines
21 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr="+wavefrontsize32" -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE32 %s
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---
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name: and_s1_vcc_vcc_vcc
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; WAVE64-LABEL: name: and_s1_vcc_vcc_vcc
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; WAVE64: liveins: $vgpr0, $vgpr1
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
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; WAVE64: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
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; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc
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; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
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; WAVE32-LABEL: name: and_s1_vcc_vcc_vcc
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; WAVE32: liveins: $vgpr0, $vgpr1
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; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
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; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
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; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc
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; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_CONSTANT i32 0
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%3:vcc(s1) = G_ICMP intpred(eq), %0, %2
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%4:vcc(s1) = G_ICMP intpred(eq), %1, %2
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%5:vcc(s1) = G_AND %3, %4
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S_ENDPGM 0, implicit %5
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...
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# Should fail to select
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---
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name: and_s1_sgpr_sgpr_sgpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; WAVE64-LABEL: name: and_s1_sgpr_sgpr_sgpr
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; WAVE64: liveins: $sgpr0, $sgpr1
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; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
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; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]]
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; WAVE32-LABEL: name: and_s1_sgpr_sgpr_sgpr
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; WAVE32: liveins: $sgpr0, $sgpr1
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; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
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; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s1) = G_TRUNC %0
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%3:sgpr(s1) = G_TRUNC %1
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%4:sgpr(s1) = G_AND %2, %3
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S_ENDPGM 0, implicit %4
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...
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---
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name: and_s16_sgpr_sgpr_sgpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; WAVE64-LABEL: name: and_s16_sgpr_sgpr_sgpr
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; WAVE64: liveins: $sgpr0, $sgpr1
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; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
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; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]]
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; WAVE32-LABEL: name: and_s16_sgpr_sgpr_sgpr
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; WAVE32: liveins: $sgpr0, $sgpr1
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; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
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; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s16) = G_TRUNC %0
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%3:sgpr(s16) = G_TRUNC %1
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%4:sgpr(s16) = G_AND %2, %3
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S_ENDPGM 0, implicit %4
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...
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---
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name: and_s16_vgpr_vgpr_vgpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; WAVE64-LABEL: name: and_s16_vgpr_vgpr_vgpr
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; WAVE64: liveins: $vgpr0, $vgpr1
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE64: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
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; WAVE32-LABEL: name: and_s16_vgpr_vgpr_vgpr
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; WAVE32: liveins: $vgpr0, $vgpr1
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; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE32: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s16) = G_TRUNC %0
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%3:vgpr(s16) = G_TRUNC %1
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%4:vgpr(s16) = G_AND %2, %3
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S_ENDPGM 0, implicit %4
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...
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---
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name: and_s32_sgpr_sgpr_sgpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; WAVE64-LABEL: name: and_s32_sgpr_sgpr_sgpr
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; WAVE64: liveins: $sgpr0, $sgpr1
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; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
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; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]]
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; WAVE32-LABEL: name: and_s32_sgpr_sgpr_sgpr
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; WAVE32: liveins: $sgpr0, $sgpr1
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; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
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; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = G_AND %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: and_s64_sgpr_sgpr_sgpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
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; WAVE64-LABEL: name: and_s64_sgpr_sgpr_sgpr
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; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
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; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; WAVE64: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
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; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[COPY1]], implicit-def $scc
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; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
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; WAVE32-LABEL: name: and_s64_sgpr_sgpr_sgpr
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; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
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; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; WAVE32: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
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; WAVE32: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[COPY1]], implicit-def $scc
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; WAVE32: S_ENDPGM 0, implicit [[S_AND_B64_]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:sgpr(s64) = COPY $sgpr2_sgpr3
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%2:sgpr(s64) = G_AND %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: and_v2s16_sgpr_sgpr_sgpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; WAVE64-LABEL: name: and_v2s16_sgpr_sgpr_sgpr
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; WAVE64: liveins: $sgpr0, $sgpr1
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; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
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; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]]
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; WAVE32-LABEL: name: and_v2s16_sgpr_sgpr_sgpr
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; WAVE32: liveins: $sgpr0, $sgpr1
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; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
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; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
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%0:sgpr(<2 x s16>) = COPY $sgpr0
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%1:sgpr(<2 x s16>) = COPY $sgpr1
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%2:sgpr(<2 x s16>) = G_AND %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: and_v2s32_sgpr_sgpr_sgpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
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; WAVE64-LABEL: name: and_v2s32_sgpr_sgpr_sgpr
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; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
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; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; WAVE64: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
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; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
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; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
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; WAVE32-LABEL: name: and_v2s32_sgpr_sgpr_sgpr
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; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
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; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; WAVE32: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
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; WAVE32: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
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; WAVE32: S_ENDPGM 0, implicit [[S_AND_B64_]]
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%0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
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%1:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
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%2:sgpr(<2 x s32>) = G_AND %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: and_v4s16_sgpr_sgpr_sgpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
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; WAVE64-LABEL: name: and_v4s16_sgpr_sgpr_sgpr
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; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
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; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; WAVE64: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
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|
|
; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
|
||
|
|
; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
|
||
|
|
; WAVE32-LABEL: name: and_v4s16_sgpr_sgpr_sgpr
|
||
|
|
; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
|
||
|
|
; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||
|
|
; WAVE32: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
|
||
|
|
; WAVE32: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
|
||
|
|
; WAVE32: S_ENDPGM 0, implicit [[S_AND_B64_]]
|
||
|
|
%0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
|
||
|
|
%1:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
|
||
|
|
%2:sgpr(<4 x s16>) = G_AND %0, %1
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: and_s32_vgpr_vgpr_vgpr
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0, $vgpr1
|
||
|
|
; WAVE64-LABEL: name: and_s32_vgpr_vgpr_vgpr
|
||
|
|
; WAVE64: liveins: $vgpr0, $vgpr1
|
||
|
|
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||
|
|
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||
|
|
; WAVE64: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
|
||
|
|
; WAVE64: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
|
||
|
|
; WAVE32-LABEL: name: and_s32_vgpr_vgpr_vgpr
|
||
|
|
; WAVE32: liveins: $vgpr0, $vgpr1
|
||
|
|
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||
|
|
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||
|
|
; WAVE32: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
|
||
|
|
; WAVE32: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
|
||
|
|
%0:vgpr(s32) = COPY $vgpr0
|
||
|
|
%1:vgpr(s32) = COPY $vgpr1
|
||
|
|
%2:vgpr(s32) = G_AND %0, %1
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: and_v2s16_vgpr_vgpr_vgpr
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0, $vgpr1
|
||
|
|
; WAVE64-LABEL: name: and_v2s16_vgpr_vgpr_vgpr
|
||
|
|
; WAVE64: liveins: $vgpr0, $vgpr1
|
||
|
|
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||
|
|
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||
|
|
; WAVE64: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
|
||
|
|
; WAVE64: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
|
||
|
|
; WAVE32-LABEL: name: and_v2s16_vgpr_vgpr_vgpr
|
||
|
|
; WAVE32: liveins: $vgpr0, $vgpr1
|
||
|
|
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||
|
|
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||
|
|
; WAVE32: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
|
||
|
|
; WAVE32: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
|
||
|
|
%0:vgpr(<2 x s16>) = COPY $vgpr0
|
||
|
|
%1:vgpr(<2 x s16>) = COPY $vgpr1
|
||
|
|
%2:vgpr(<2 x s16>) = G_AND %0, %1
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
|
||
|
|
# This should fail to select
|
||
|
|
---
|
||
|
|
|
||
|
|
name: and_s64_vgpr_vgpr_vgpr
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||
|
|
; WAVE64-LABEL: name: and_s64_vgpr_vgpr_vgpr
|
||
|
|
; WAVE64: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||
|
|
; WAVE64: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
|
||
|
|
; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
|
||
|
|
; WAVE64: [[AND:%[0-9]+]]:vgpr(s64) = G_AND [[COPY]], [[COPY1]]
|
||
|
|
; WAVE64: S_ENDPGM 0, implicit [[AND]](s64)
|
||
|
|
; WAVE32-LABEL: name: and_s64_vgpr_vgpr_vgpr
|
||
|
|
; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||
|
|
; WAVE32: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
|
||
|
|
; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
|
||
|
|
; WAVE32: [[AND:%[0-9]+]]:vgpr(s64) = G_AND [[COPY]], [[COPY1]]
|
||
|
|
; WAVE32: S_ENDPGM 0, implicit [[AND]](s64)
|
||
|
|
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||
|
|
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||
|
|
%2:vgpr(s64) = G_AND %0, %1
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: and_s1_vcc_copy_to_vcc
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0, $vgpr1
|
||
|
|
; WAVE64-LABEL: name: and_s1_vcc_copy_to_vcc
|
||
|
|
; WAVE64: liveins: $vgpr0, $vgpr1
|
||
|
|
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||
|
|
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||
|
|
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||
|
|
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||
|
|
; WAVE64: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
|
||
|
|
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
|
||
|
|
; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
|
||
|
|
; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
|
||
|
|
; WAVE32-LABEL: name: and_s1_vcc_copy_to_vcc
|
||
|
|
; WAVE32: liveins: $vgpr0, $vgpr1
|
||
|
|
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||
|
|
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||
|
|
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||
|
|
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||
|
|
; WAVE32: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
|
||
|
|
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
|
||
|
|
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
|
||
|
|
; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
|
||
|
|
%0:vgpr(s32) = COPY $vgpr0
|
||
|
|
%1:vgpr(s32) = COPY $vgpr1
|
||
|
|
%2:vgpr(s1) = G_TRUNC %0
|
||
|
|
%3:vgpr(s1) = G_TRUNC %1
|
||
|
|
%4:vcc(s1) = COPY %2
|
||
|
|
%5:vcc(s1) = COPY %3
|
||
|
|
%6:vcc(s1) = G_AND %4, %5
|
||
|
|
S_ENDPGM 0, implicit %6
|
||
|
|
...
|
||
|
|
|
||
|
|
# The selector for the copy of the and result may constrain the result
|
||
|
|
# register of the and, losing that it is a VCCRegBank context.
|
||
|
|
|
||
|
|
# Works for wave32, should fail for wave64
|
||
|
|
---
|
||
|
|
name: copy_select_constrain_vcc_result_reg_wave32
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0, $sgpr0
|
||
|
|
|
||
|
|
; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
|
||
|
|
; WAVE64: liveins: $vgpr0, $sgpr0
|
||
|
|
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||
|
|
; WAVE64: %sgpr0:sreg_32 = COPY $sgpr0
|
||
|
|
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||
|
|
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||
|
|
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
|
||
|
|
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
||
|
|
; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
|
||
|
|
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B64_]]
|
||
|
|
; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
|
||
|
|
; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
|
||
|
|
; WAVE32: liveins: $vgpr0, $sgpr0
|
||
|
|
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||
|
|
; WAVE32: %sgpr0:sreg_32 = COPY $sgpr0
|
||
|
|
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||
|
|
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||
|
|
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
|
||
|
|
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
||
|
|
; WAVE32: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
|
||
|
|
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_1]]
|
||
|
|
; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
|
||
|
|
%1:vgpr(s32) = COPY $vgpr0
|
||
|
|
%0:vgpr(s1) = G_TRUNC %1(s32)
|
||
|
|
%sgpr0:sgpr(s32) = COPY $sgpr0
|
||
|
|
%2:sgpr(s1) = G_TRUNC %sgpr0
|
||
|
|
%6:sgpr(s32) = G_CONSTANT i32 0
|
||
|
|
%7:sgpr(p1) = G_IMPLICIT_DEF
|
||
|
|
%9:vcc(s1) = COPY %0(s1)
|
||
|
|
%10:vcc(s1) = COPY %2(s1)
|
||
|
|
%8:vcc(s1) = G_AND %9, %10
|
||
|
|
%3:sreg_32_xm0(s1) = COPY %8(s1)
|
||
|
|
S_ENDPGM 0, implicit %3
|
||
|
|
|
||
|
|
...
|
||
|
|
|
||
|
|
# Works for wave64, should fail for wave32
|
||
|
|
---
|
||
|
|
name: copy_select_constrain_vcc_result_reg_wave64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0, $sgpr0
|
||
|
|
|
||
|
|
; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
|
||
|
|
; WAVE64: liveins: $vgpr0, $sgpr0
|
||
|
|
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||
|
|
; WAVE64: %sgpr0:sreg_32 = COPY $sgpr0
|
||
|
|
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||
|
|
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||
|
|
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
|
||
|
|
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
||
|
|
; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
|
||
|
|
; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_AND_B64_]]
|
||
|
|
; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
|
||
|
|
; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
|
||
|
|
; WAVE32: liveins: $vgpr0, $sgpr0
|
||
|
|
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||
|
|
; WAVE32: %sgpr0:sreg_32 = COPY $sgpr0
|
||
|
|
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||
|
|
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||
|
|
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
|
||
|
|
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
||
|
|
; WAVE32: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
|
||
|
|
; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_AND_B32_1]]
|
||
|
|
; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
|
||
|
|
%1:vgpr(s32) = COPY $vgpr0
|
||
|
|
%0:vgpr(s1) = G_TRUNC %1(s32)
|
||
|
|
%sgpr0:sgpr(s32) = COPY $sgpr0
|
||
|
|
%2:sgpr(s1) = G_TRUNC %sgpr0
|
||
|
|
%6:sgpr(s32) = G_CONSTANT i32 0
|
||
|
|
%7:sgpr(p1) = G_IMPLICIT_DEF
|
||
|
|
%9:vcc(s1) = COPY %0(s1)
|
||
|
|
%10:vcc(s1) = COPY %2(s1)
|
||
|
|
%8:vcc(s1) = G_AND %9, %10
|
||
|
|
%3:sreg_64_xexec(s1) = COPY %8(s1)
|
||
|
|
S_ENDPGM 0, implicit %3
|
||
|
|
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
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name: and_s32_sgpr_sgpr_sgpr_result_reg_class
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; WAVE64-LABEL: name: and_s32_sgpr_sgpr_sgpr_result_reg_class
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; WAVE64: liveins: $sgpr0, $sgpr1
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; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
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; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]]
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; WAVE32-LABEL: name: and_s32_sgpr_sgpr_sgpr_result_reg_class
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; WAVE32: liveins: $sgpr0, $sgpr1
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; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||
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; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||
|
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; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
|
||
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; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
|
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%0:sgpr(s32) = COPY $sgpr0
|
||
|
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%1:sgpr(s32) = COPY $sgpr1
|
||
|
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%2:sreg_32(s32) = G_AND %0, %1
|
||
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S_ENDPGM 0, implicit %2
|
||
|
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...
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