129 lines
3.9 KiB
Plaintext
129 lines
3.9 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
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---
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name: ldexp_s32_vsv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; GCN-LABEL: name: ldexp_s32_vsv
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; GCN: liveins: $sgpr0, $vgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: %2:vgpr_32 = nofpexcept V_LDEXP_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
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; GCN: S_ENDPGM 0, implicit %2
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: ldexp_s32_vvs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; GCN-LABEL: name: ldexp_s32_vvs
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; GCN: liveins: $sgpr0, $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: %2:vgpr_32 = nofpexcept V_LDEXP_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
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; GCN: S_ENDPGM 0, implicit %2
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: ldexp_s32_vvv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GCN-LABEL: name: ldexp_s32_vvv
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; GCN: liveins: $vgpr0, $vgpr1
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: %2:vgpr_32 = nofpexcept V_LDEXP_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
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; GCN: S_ENDPGM 0, implicit %2
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: ldexp_s64_vsv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr0
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; GCN-LABEL: name: ldexp_s64_vsv
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; GCN: liveins: $sgpr0_sgpr1, $vgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: %2:vreg_64 = nofpexcept V_LDEXP_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
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; GCN: S_ENDPGM 0, implicit %2
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: ldexp_s64_vvs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr0
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; GCN-LABEL: name: ldexp_s64_vvs
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; GCN: liveins: $sgpr0_sgpr1, $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: %2:vreg_64 = nofpexcept V_LDEXP_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
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; GCN: S_ENDPGM 0, implicit %2
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: ldexp_s64_vvv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2
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; GCN-LABEL: name: ldexp_s64_vvv
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; GCN: liveins: $vgpr0_vgpr1, $vgpr2
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; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GCN: %2:vreg_64 = nofpexcept V_LDEXP_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
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; GCN: S_ENDPGM 0, implicit %2
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s32) = COPY $vgpr2
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%2:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
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S_ENDPGM 0, implicit %2
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...
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