206 lines
6.3 KiB
Plaintext
206 lines
6.3 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
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---
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name: fmed3_s32_vvvv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; GCN-LABEL: name: fmed3_s32_vvvv
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; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = COPY $vgpr2
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%3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
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S_ENDPGM 0, implicit %3
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...
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---
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name: fmed3_s32_vsvv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0, $vgpr1
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; GCN-LABEL: name: fmed3_s32_vsvv
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; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(s32) = COPY $vgpr1
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%3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
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S_ENDPGM 0, implicit %3
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...
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---
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name: fmed3_s32_vvsv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0, $vgpr1
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; GCN-LABEL: name: fmed3_s32_vvsv
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; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s32) = COPY $vgpr1
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%3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
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S_ENDPGM 0, implicit %3
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...
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---
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name: fmed3_s32_vvvs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0, $vgpr1
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; GCN-LABEL: name: fmed3_s32_vvvs
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; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:sgpr(s32) = COPY $sgpr0
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%3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
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S_ENDPGM 0, implicit %3
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...
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# Same SGPR used, so doesn't violate the constant bus restriction.
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---
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name: fmed3_s32_vssv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; GCN-LABEL: name: fmed3_s32_vssv
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; GCN: liveins: $sgpr0, $vgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: fmed3_s32_vsvs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; GCN-LABEL: name: fmed3_s32_vsvs
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; GCN: liveins: $sgpr0, $vgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %0
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S_ENDPGM 0, implicit %2
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...
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---
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name: fmed3_s32_vvss
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; GCN-LABEL: name: fmed3_s32_vvss
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; GCN: liveins: $sgpr0, $vgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %1, %0, %0
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S_ENDPGM 0, implicit %2
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...
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---
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name: fmed3_s32_vsss
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; GCN-LABEL: name: fmed3_s32_vsss
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; GCN: liveins: $sgpr0, $vgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %0, %0
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S_ENDPGM 0, implicit %1
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...
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# FIXME: This should probably have been fixed by RegBankSelect, but we should fail to select it.
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# ---
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# name: fmed3_s32_vssv_constant_bus_violation
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# legalized: true
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# regBankSelected: true
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# tracksRegLiveness: true
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# body: |
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# bb.0:
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# liveins: $sgpr0, $sgpr1, $vgpr0
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# %0:sgpr(s32) = COPY $sgpr0
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# %1:sgpr(s32) = COPY $sgpr1
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# %2:vgpr(s32) = COPY $vgpr0
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# %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
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# S_ENDPGM 0, implicit %3
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# ...
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