84 lines
2.9 KiB
LLVM
84 lines
2.9 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -O0 -global-isel -verify-machineinstrs -o - %s | FileCheck %s
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define i32 @test_sgpr_reg_class_constraint() nounwind {
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; CHECK-LABEL: test_sgpr_reg_class_constraint:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: s_mov_b32 s4, 7
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: s_mov_b32 s5, 8
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: s_add_u32 s4, s4, s5
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_mov_b32_e32 v0, s4
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind
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%asm1 = tail call i32 asm "s_mov_b32 $0, 8", "=s"() nounwind
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%asm2 = tail call i32 asm "s_add_u32 $0, $1, $2", "=s,s,s"(i32 %asm0, i32 %asm1) nounwind
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ret i32 %asm2
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}
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define i32 @test_sgpr_matching_constraint() nounwind {
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; CHECK-LABEL: test_sgpr_matching_constraint:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: s_mov_b32 s5, 7
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: s_mov_b32 s4, 8
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: s_add_u32 s4, s5, s4
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_mov_b32_e32 v0, s4
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind
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%asm1 = tail call i32 asm "s_mov_b32 $0, 8", "=s"() nounwind
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%asm2 = tail call i32 asm "s_add_u32 $0, $1, $2", "=s,s,0"(i32 %asm0, i32 %asm1) nounwind
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ret i32 %asm2
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}
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define i32 @test_sgpr_to_vgpr_move_reg_class_constraint() nounwind {
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; CHECK-LABEL: test_sgpr_to_vgpr_move_reg_class_constraint:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: s_mov_b32 s4, 7
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: v_mov_b32 v0, s4
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind
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%asm1 = tail call i32 asm "v_mov_b32 $0, $1", "=v,s"(i32 %asm0) nounwind
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ret i32 %asm1
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}
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define i32 @test_sgpr_to_vgpr_move_matching_constraint() nounwind {
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; CHECK-LABEL: test_sgpr_to_vgpr_move_matching_constraint:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: s_mov_b32 s4, 7
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_mov_b32_e32 v0, s4
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: v_mov_b32 v0, v0
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind
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%asm1 = tail call i32 asm "v_mov_b32 $0, $1", "=v,0"(i32 %asm0) nounwind
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ret i32 %asm1
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}
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!0 = !{i32 70}
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