141 lines
6.8 KiB
LLVM
141 lines
6.8 KiB
LLVM
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; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs -o - %s | FileCheck %s
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@lds0 = addrspace(3) global [512 x float] undef
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@lds1 = addrspace(3) global [256 x float] undef
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@lds2 = addrspace(3) global [4096 x float] undef
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@lds3 = addrspace(3) global [67 x i8] undef
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@dynamic_shared0 = external addrspace(3) global [0 x float]
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@dynamic_shared1 = external addrspace(3) global [0 x double]
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@dynamic_shared2 = external addrspace(3) global [0 x double], align 4
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@dynamic_shared3 = external addrspace(3) global [0 x double], align 16
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; CHECK-LABEL: {{^}}dynamic_shared_array_0:
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; CHECK: v_add_u32_e32 v{{[0-9]+}}, 0x800, v{{[0-9]+}}
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define amdgpu_kernel void @dynamic_shared_array_0(float addrspace(1)* %out) {
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%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds0, i32 0, i32 %tid.x
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%val0 = load float, float addrspace(3)* %arrayidx0, align 4
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%arrayidx1 = getelementptr inbounds [0 x float], [0 x float] addrspace(3)* @dynamic_shared0, i32 0, i32 %tid.x
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store float %val0, float addrspace(3)* %arrayidx1, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}dynamic_shared_array_1:
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; CHECK: v_lshlrev_b32_e32 {{v[0-9]+}}, 2, {{v[0-9]+}}
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; CHECK: v_lshlrev_b32_e32 {{v[0-9]+}}, 2, {{v[0-9]+}}
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; CHECK: v_lshlrev_b32_e32 [[IDX:v[0-9]+]], 2, {{v[0-9]+}}
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; CHECK: v_add_u32_e32 {{v[0-9]+}}, 0xc00, [[IDX]]
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define amdgpu_kernel void @dynamic_shared_array_1(float addrspace(1)* %out, i32 %cond) {
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entry:
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%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%idx.0 = add nsw i32 %tid.x, 64
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%tmp = icmp eq i32 %cond, 0
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br i1 %tmp, label %if, label %else
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if: ; preds = %entry
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%arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0
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%val0 = load float, float addrspace(3)* %arrayidx0, align 4
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br label %endif
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else: ; preds = %entry
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%arrayidx1 = getelementptr inbounds [256 x float], [256 x float] addrspace(3)* @lds1, i32 0, i32 %idx.0
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%val1 = load float, float addrspace(3)* %arrayidx1, align 4
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br label %endif
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endif: ; preds = %else, %if
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%val = phi float [ %val0, %if ], [ %val1, %else ]
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%arrayidx = getelementptr inbounds [0 x float], [0 x float] addrspace(3)* @dynamic_shared0, i32 0, i32 %tid.x
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store float %val, float addrspace(3)* %arrayidx, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}dynamic_shared_array_2:
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; CHECK: v_lshlrev_b32_e32 [[IDX:v[0-9]+]], 2, {{v[0-9]+}}
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; CHECK: v_add_u32_e32 {{v[0-9]+}}, 0x4000, [[IDX]]
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define amdgpu_kernel void @dynamic_shared_array_2(i32 %idx) {
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%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%vidx = add i32 %tid.x, %idx
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%arrayidx0 = getelementptr inbounds [4096 x float], [4096 x float] addrspace(3)* @lds2, i32 0, i32 %vidx
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%val0 = load float, float addrspace(3)* %arrayidx0, align 4
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%arrayidx1 = getelementptr inbounds [0 x float], [0 x float] addrspace(3)* @dynamic_shared0, i32 0, i32 %tid.x
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store float %val0, float addrspace(3)* %arrayidx1, align 4
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ret void
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}
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; The offset to the dynamic shared memory array should be aligned on the type
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; specified.
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; CHECK-LABEL: {{^}}dynamic_shared_array_3:
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; CHECK: v_lshlrev_b32_e32 [[IDX:v[0-9]+]], 2, {{v[0-9]+}}
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; CHECK: v_add_u32_e32 {{v[0-9]+}}, 0x44, [[IDX]]
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define amdgpu_kernel void @dynamic_shared_array_3(i32 %idx) {
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%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%vidx = add i32 %tid.x, %idx
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%arrayidx0 = getelementptr inbounds [67 x i8], [67 x i8] addrspace(3)* @lds3, i32 0, i32 %vidx
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%val0 = load i8, i8 addrspace(3)* %arrayidx0, align 4
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%val1 = uitofp i8 %val0 to float
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%arrayidx1 = getelementptr inbounds [0 x float], [0 x float] addrspace(3)* @dynamic_shared0, i32 0, i32 %tid.x
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store float %val1, float addrspace(3)* %arrayidx1, align 4
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ret void
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}
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; The offset to the dynamic shared memory array should be aligned on the
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; maximal one.
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; CHECK-LABEL: {{^}}dynamic_shared_array_4:
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; CHECK: v_mov_b32_e32 [[DYNLDS:v[0-9]+]], 0x48
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; CHECK: v_lshlrev_b32_e32 [[IDX:v[0-9]+]], 2, {{v[0-9]+}}
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; CHECK: v_add_u32_e32 {{v[0-9]+}}, [[DYNLDS]], [[IDX]]
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define amdgpu_kernel void @dynamic_shared_array_4(i32 %idx) {
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%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%vidx = add i32 %tid.x, %idx
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%arrayidx0 = getelementptr inbounds [67 x i8], [67 x i8] addrspace(3)* @lds3, i32 0, i32 %vidx
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%val0 = load i8, i8 addrspace(3)* %arrayidx0, align 4
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%val1 = uitofp i8 %val0 to float
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%val2 = uitofp i8 %val0 to double
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%arrayidx1 = getelementptr inbounds [0 x float], [0 x float] addrspace(3)* @dynamic_shared0, i32 0, i32 %tid.x
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store float %val1, float addrspace(3)* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds [0 x double], [0 x double] addrspace(3)* @dynamic_shared1, i32 0, i32 %tid.x
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store double %val2, double addrspace(3)* %arrayidx2, align 4
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ret void
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}
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; Honor the explicit alignment from the specified variable.
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; CHECK-LABEL: {{^}}dynamic_shared_array_5:
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; CHECK: v_mov_b32_e32 [[DYNLDS:v[0-9]+]], 0x44
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; CHECK: v_lshlrev_b32_e32 [[IDX:v[0-9]+]], 2, {{v[0-9]+}}
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; CHECK: v_add_u32_e32 {{v[0-9]+}}, [[DYNLDS]], [[IDX]]
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define amdgpu_kernel void @dynamic_shared_array_5(i32 %idx) {
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%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%vidx = add i32 %tid.x, %idx
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%arrayidx0 = getelementptr inbounds [67 x i8], [67 x i8] addrspace(3)* @lds3, i32 0, i32 %vidx
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%val0 = load i8, i8 addrspace(3)* %arrayidx0, align 4
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%val1 = uitofp i8 %val0 to float
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%val2 = uitofp i8 %val0 to double
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%arrayidx1 = getelementptr inbounds [0 x float], [0 x float] addrspace(3)* @dynamic_shared0, i32 0, i32 %tid.x
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store float %val1, float addrspace(3)* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds [0 x double], [0 x double] addrspace(3)* @dynamic_shared2, i32 0, i32 %tid.x
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store double %val2, double addrspace(3)* %arrayidx2, align 4
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ret void
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}
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; Honor the explicit alignment from the specified variable.
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; CHECK-LABEL: {{^}}dynamic_shared_array_6:
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; CHECK: v_mov_b32_e32 [[DYNLDS:v[0-9]+]], 0x50
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; CHECK: v_lshlrev_b32_e32 [[IDX:v[0-9]+]], 2, {{v[0-9]+}}
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; CHECK: v_add_u32_e32 {{v[0-9]+}}, [[DYNLDS]], [[IDX]]
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define amdgpu_kernel void @dynamic_shared_array_6(i32 %idx) {
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%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%vidx = add i32 %tid.x, %idx
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%arrayidx0 = getelementptr inbounds [67 x i8], [67 x i8] addrspace(3)* @lds3, i32 0, i32 %vidx
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%val0 = load i8, i8 addrspace(3)* %arrayidx0, align 4
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%val1 = uitofp i8 %val0 to float
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%val2 = uitofp i8 %val0 to double
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%arrayidx1 = getelementptr inbounds [0 x float], [0 x float] addrspace(3)* @dynamic_shared0, i32 0, i32 %tid.x
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store float %val1, float addrspace(3)* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds [0 x double], [0 x double] addrspace(3)* @dynamic_shared3, i32 0, i32 %tid.x
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store double %val2, double addrspace(3)* %arrayidx2, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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