129 lines
7.3 KiB
LLVM
129 lines
7.3 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -stop-after=legalizer < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -stop-after=legalizer < %s | FileCheck -check-prefix=GCN %s
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@external_constant = external addrspace(4) constant i32, align 4
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@external_constant32 = external addrspace(6) constant i32, align 4
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@external_global = external addrspace(1) global i32, align 4
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@external_other = external addrspace(999) global i32, align 4
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@internal_constant = internal addrspace(4) constant i32 9, align 4
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@internal_constant32 = internal addrspace(6) constant i32 9, align 4
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@internal_global = internal addrspace(1) global i32 9, align 4
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@internal_other = internal addrspace(999) global i32 9, align 4
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define i32 addrspace(4)* @external_constant_got() {
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; GCN-LABEL: name: external_constant_got
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; GCN: bb.1 (%ir-block.0):
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; GCN: liveins: $sgpr30_sgpr31
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; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant + 4, target-flags(amdgpu-gotprel32-hi) @external_constant + 12, implicit-def $scc
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; GCN: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load 8 from got, addrspace 4)
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; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p4)
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; GCN: $vgpr0 = COPY [[UV]](s32)
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; GCN: $vgpr1 = COPY [[UV1]](s32)
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; GCN: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
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; GCN: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
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ret i32 addrspace(4)* @external_constant
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}
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define i32 addrspace(1)* @external_global_got() {
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; GCN-LABEL: name: external_global_got
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; GCN: bb.1 (%ir-block.0):
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; GCN: liveins: $sgpr30_sgpr31
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; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_global + 4, target-flags(amdgpu-gotprel32-hi) @external_global + 12, implicit-def $scc
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; GCN: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load 8 from got, addrspace 4)
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; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p1)
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; GCN: $vgpr0 = COPY [[UV]](s32)
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; GCN: $vgpr1 = COPY [[UV1]](s32)
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; GCN: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
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; GCN: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
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ret i32 addrspace(1)* @external_global
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}
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define i32 addrspace(999)* @external_other_got() {
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; GCN-LABEL: name: external_other_got
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; GCN: bb.1 (%ir-block.0):
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; GCN: liveins: $sgpr30_sgpr31
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; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_other + 4, target-flags(amdgpu-gotprel32-hi) @external_other + 12, implicit-def $scc
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; GCN: [[LOAD:%[0-9]+]]:_(p999) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load 8 from got, addrspace 4)
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; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p999)
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; GCN: $vgpr0 = COPY [[UV]](s32)
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; GCN: $vgpr1 = COPY [[UV1]](s32)
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; GCN: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
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; GCN: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
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ret i32 addrspace(999)* @external_other
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}
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define i32 addrspace(4)* @internal_constant_pcrel() {
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; GCN-LABEL: name: internal_constant_pcrel
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; GCN: bb.1 (%ir-block.0):
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; GCN: liveins: $sgpr30_sgpr31
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; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_constant + 4, target-flags(amdgpu-rel32-hi) @internal_constant + 12, implicit-def $scc
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; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p4)
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; GCN: $vgpr0 = COPY [[UV]](s32)
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; GCN: $vgpr1 = COPY [[UV1]](s32)
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; GCN: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
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; GCN: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
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ret i32 addrspace(4)* @internal_constant
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}
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define i32 addrspace(1)* @internal_global_pcrel() {
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; GCN-LABEL: name: internal_global_pcrel
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; GCN: bb.1 (%ir-block.0):
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; GCN: liveins: $sgpr30_sgpr31
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; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p1) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_global + 4, target-flags(amdgpu-rel32-hi) @internal_global + 12, implicit-def $scc
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; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p1)
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; GCN: $vgpr0 = COPY [[UV]](s32)
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; GCN: $vgpr1 = COPY [[UV1]](s32)
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; GCN: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
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; GCN: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
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ret i32 addrspace(1)* @internal_global
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}
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define i32 addrspace(999)* @internal_other_pcrel() {
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; GCN-LABEL: name: internal_other_pcrel
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; GCN: bb.1 (%ir-block.0):
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; GCN: liveins: $sgpr30_sgpr31
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; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p999) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_other + 4, target-flags(amdgpu-rel32-hi) @internal_other + 12, implicit-def $scc
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; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p999)
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; GCN: $vgpr0 = COPY [[UV]](s32)
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; GCN: $vgpr1 = COPY [[UV1]](s32)
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; GCN: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
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; GCN: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
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ret i32 addrspace(999)* @internal_other
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}
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define i32 addrspace(6)* @external_constant32_got() {
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; GCN-LABEL: name: external_constant32_got
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; GCN: bb.1 (%ir-block.0):
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; GCN: liveins: $sgpr30_sgpr31
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; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant32 + 4, target-flags(amdgpu-gotprel32-hi) @external_constant32 + 12, implicit-def $scc
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; GCN: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load 8 from got, addrspace 4)
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; GCN: [[EXTRACT:%[0-9]+]]:_(p6) = G_EXTRACT [[LOAD]](p4), 0
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; GCN: $vgpr0 = COPY [[EXTRACT]](p6)
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; GCN: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
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; GCN: S_SETPC_B64_return [[COPY1]], implicit $vgpr0
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ret i32 addrspace(6)* @external_constant32
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}
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define i32 addrspace(6)* @internal_constant32_pcrel() {
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; GCN-LABEL: name: internal_constant32_pcrel
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; GCN: bb.1 (%ir-block.0):
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; GCN: liveins: $sgpr30_sgpr31
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; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_constant32 + 4, target-flags(amdgpu-rel32-hi) @internal_constant32 + 12, implicit-def $scc
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; GCN: [[EXTRACT:%[0-9]+]]:_(p6) = G_EXTRACT [[SI_PC_ADD_REL_OFFSET]](p4), 0
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; GCN: $vgpr0 = COPY [[EXTRACT]](p6)
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; GCN: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
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; GCN: S_SETPC_B64_return [[COPY1]], implicit $vgpr0
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ret i32 addrspace(6)* @internal_constant32
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}
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