92 lines
4.3 KiB
LLVM
92 lines
4.3 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -stop-after=legalizer -o - %s | FileCheck %s
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; Make sure legalizer info doesn't assert on dummy targets
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define i16 @vop3p_add_i16(i16 %arg0) #0 {
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; CHECK-LABEL: name: vop3p_add_i16
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[TRUNC]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16)
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; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
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%add = add i16 %arg0, %arg0
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ret i16 %add
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}
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define <2 x i16> @vop3p_add_v2i16(<2 x i16> %arg0) #0 {
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; CHECK-LABEL: name: vop3p_add_v2i16
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
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; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
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; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
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; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
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; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
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; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
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; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
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; CHECK: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[TRUNC2]]
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; CHECK: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[TRUNC1]], [[TRUNC3]]
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; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ADD]](s16)
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; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ADD1]](s16)
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; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
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; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
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; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
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; CHECK: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
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; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
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%add = add <2 x i16> %arg0, %arg0
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ret <2 x i16> %add
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}
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define i16 @halfinsts_add_i16(i16 %arg0) #1 {
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; CHECK-LABEL: name: halfinsts_add_i16
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY2]]
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
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; CHECK: $vgpr0 = COPY [[COPY3]](s32)
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; CHECK: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK: S_SETPC_B64_return [[COPY4]], implicit $vgpr0
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%add = add i16 %arg0, %arg0
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ret i16 %add
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}
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define <2 x i16> @halfinsts_add_v2i16(<2 x i16> %arg0) #1 {
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; CHECK-LABEL: name: halfinsts_add_v2i16
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY3]], [[COPY4]]
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; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY5]], [[COPY6]]
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; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
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; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
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; CHECK: $vgpr0 = COPY [[COPY7]](s32)
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; CHECK: $vgpr1 = COPY [[COPY8]](s32)
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; CHECK: [[COPY9:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
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; CHECK: S_SETPC_B64_return [[COPY9]], implicit $vgpr0, implicit $vgpr1
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%add = add <2 x i16> %arg0, %arg0
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ret <2 x i16> %add
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}
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attributes #0 = { "target-features"="+vop3p" }
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attributes #0 = { "target-features"="+16-bit-insts" }
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