221 lines
7.2 KiB
LLVM
221 lines
7.2 KiB
LLVM
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+v8.2a,+fullfp16 -fp-contract=fast | FileCheck %s
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define half @test_FMULADDH_OP1(half %a, half %b, half %c) {
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; CHECK-LABEL: test_FMULADDH_OP1:
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; CHECK: fmadd {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
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entry:
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%mul = fmul fast half %c, %b
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%add = fadd fast half %mul, %a
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ret half %add
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}
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define half @test_FMULADDH_OP2(half %a, half %b, half %c) {
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; CHECK-LABEL: test_FMULADDH_OP2:
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; CHECK: fmadd {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
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entry:
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%mul = fmul fast half %c, %b
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%add = fadd fast half %a, %mul
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ret half %add
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}
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define half @test_FMULSUBH_OP1(half %a, half %b, half %c) {
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; CHECK-LABEL: test_FMULSUBH_OP1:
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; CHECK: fnmsub {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
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entry:
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%mul = fmul fast half %c, %b
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%sub = fsub fast half %mul, %a
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ret half %sub
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}
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define half @test_FMULSUBH_OP2(half %a, half %b, half %c) {
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; CHECK-LABEL: test_FMULSUBH_OP2:
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; CHECK: fmsub {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
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entry:
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%mul = fmul fast half %c, %b
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%add = fsub fast half %a, %mul
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ret half %add
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}
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define half @test_FNMULSUBH_OP1(half %a, half %b, half %c) {
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; CHECK-LABEL: test_FNMULSUBH_OP1:
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; CHECK: fnmadd {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
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entry:
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%mul = fmul fast half %c, %b
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%neg = fsub fast half -0.0, %mul
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%add = fsub fast half %neg, %a
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ret half %add
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}
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define <4 x half> @test_FMLAv4f16_OP1(<4 x half> %a, <4 x half> %b, <4 x half> %c) {
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; CHECK-LABEL: test_FMLAv4f16_OP1:
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; CHECK: fmla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
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entry:
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%mul = fmul fast <4 x half> %c, %b
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%add = fadd fast <4 x half> %mul, %a
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ret <4 x half> %add
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}
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define <4 x half> @test_FMLAv4f16_OP2(<4 x half> %a, <4 x half> %b, <4 x half> %c) {
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; CHECK-LABEL: test_FMLAv4f16_OP2:
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; CHECK: fmla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
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entry:
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%mul = fmul fast <4 x half> %c, %b
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%add = fadd fast <4 x half> %a, %mul
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ret <4 x half> %add
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}
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define <8 x half> @test_FMLAv8f16_OP1(<8 x half> %a, <8 x half> %b, <8 x half> %c) {
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; CHECK-LABEL: test_FMLAv8f16_OP1:
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; CHECK: fmla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
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entry:
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%mul = fmul fast <8 x half> %c, %b
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%add = fadd fast <8 x half> %mul, %a
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ret <8 x half> %add
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}
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define <8 x half> @test_FMLAv8f16_OP2(<8 x half> %a, <8 x half> %b, <8 x half> %c) {
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; CHECK-LABEL: test_FMLAv8f16_OP2:
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; CHECK: fmla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
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entry:
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%mul = fmul fast <8 x half> %c, %b
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%add = fadd fast <8 x half> %a, %mul
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ret <8 x half> %add
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}
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define <4 x half> @test_FMLAv4i16_indexed_OP1(<4 x half> %a, <4 x i16> %b, <4 x i16> %c) {
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; CHECK-LABEL: test_FMLAv4i16_indexed_OP1:
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; CHECK-FIXME: Currently LLVM produces inefficient code:
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; CHECK: mul
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; CHECK: fadd
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; CHECK-FIXME: It should instead produce the following instruction:
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; CHECK-FIXME: fmla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
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entry:
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%mul = mul <4 x i16> %c, %b
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%m = bitcast <4 x i16> %mul to <4 x half>
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%add = fadd fast <4 x half> %m, %a
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ret <4 x half> %add
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}
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define <4 x half> @test_FMLAv4i16_indexed_OP2(<4 x half> %a, <4 x i16> %b, <4 x i16> %c) {
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; CHECK-LABEL: test_FMLAv4i16_indexed_OP2:
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; CHECK-FIXME: Currently LLVM produces inefficient code:
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; CHECK: mul
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; CHECK: fadd
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; CHECK-FIXME: It should instead produce the following instruction:
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; CHECK-FIXME: fmla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
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entry:
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%mul = mul <4 x i16> %c, %b
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%m = bitcast <4 x i16> %mul to <4 x half>
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%add = fadd fast <4 x half> %a, %m
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ret <4 x half> %add
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}
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define <8 x half> @test_FMLAv8i16_indexed_OP1(<8 x half> %a, <8 x i16> %b, <8 x i16> %c) {
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; CHECK-LABEL: test_FMLAv8i16_indexed_OP1:
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; CHECK-FIXME: Currently LLVM produces inefficient code:
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; CHECK: mul
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; CHECK: fadd
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; CHECK-FIXME: It should instead produce the following instruction:
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; CHECK-FIXME: fmla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
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entry:
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%mul = mul <8 x i16> %c, %b
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%m = bitcast <8 x i16> %mul to <8 x half>
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%add = fadd fast <8 x half> %m, %a
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ret <8 x half> %add
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}
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define <8 x half> @test_FMLAv8i16_indexed_OP2(<8 x half> %a, <8 x i16> %b, <8 x i16> %c) {
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; CHECK-LABEL: test_FMLAv8i16_indexed_OP2:
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; CHECK-FIXME: Currently LLVM produces inefficient code:
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; CHECK: mul
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; CHECK: fadd
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; CHECK-FIXME: It should instead produce the following instruction:
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; CHECK-FIXME: fmla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
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entry:
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%mul = mul <8 x i16> %c, %b
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%m = bitcast <8 x i16> %mul to <8 x half>
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%add = fadd fast <8 x half> %a, %m
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ret <8 x half> %add
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}
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define <4 x half> @test_FMLSv4f16_OP1(<4 x half> %a, <4 x half> %b, <4 x half> %c) {
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; CHECK-LABEL: test_FMLSv4f16_OP1:
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; CHECK: fneg {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
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; CHECK: fmla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
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entry:
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%mul = fmul fast <4 x half> %c, %b
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%sub = fsub fast <4 x half> %mul, %a
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ret <4 x half> %sub
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}
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define <4 x half> @test_FMLSv4f16_OP2(<4 x half> %a, <4 x half> %b, <4 x half> %c) {
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; CHECK-LABEL: test_FMLSv4f16_OP2:
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; CHECK: fmls {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
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entry:
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%mul = fmul fast <4 x half> %c, %b
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%sub = fsub fast <4 x half> %a, %mul
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ret <4 x half> %sub
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}
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define <8 x half> @test_FMLSv8f16_OP1(<8 x half> %a, <8 x half> %b, <8 x half> %c) {
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; CHECK-LABEL: test_FMLSv8f16_OP1:
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; CHECK: fneg {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
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; CHECK: fmla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
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entry:
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%mul = fmul fast <8 x half> %c, %b
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%sub = fsub fast <8 x half> %mul, %a
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ret <8 x half> %sub
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}
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define <8 x half> @test_FMLSv8f16_OP2(<8 x half> %a, <8 x half> %b, <8 x half> %c) {
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; CHECK-LABEL: test_FMLSv8f16_OP2:
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; CHECK: fmls {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
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entry:
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%mul = fmul fast <8 x half> %c, %b
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%sub = fsub fast <8 x half> %a, %mul
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ret <8 x half> %sub
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}
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define <4 x half> @test_FMLSv4i16_indexed_OP2(<4 x half> %a, <4 x i16> %b, <4 x i16> %c) {
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; CHECK-LABEL: test_FMLSv4i16_indexed_OP2:
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; CHECK-FIXME: Currently LLVM produces inefficient code:
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; CHECK: mul
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; CHECK: fsub
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; CHECK-FIXME: It should instead produce the following instruction:
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; CHECK-FIXME: fmls {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
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entry:
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%mul = mul <4 x i16> %c, %b
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%m = bitcast <4 x i16> %mul to <4 x half>
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%sub = fsub fast <4 x half> %a, %m
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ret <4 x half> %sub
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}
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define <8 x half> @test_FMLSv8i16_indexed_OP1(<8 x half> %a, <8 x i16> %b, <8 x i16> %c) {
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; CHECK-LABEL: test_FMLSv8i16_indexed_OP1:
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; CHECK-FIXME: Currently LLVM produces inefficient code:
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; CHECK: mul
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; CHECK: fsub
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; CHECK-FIXME: It should instead produce the following instruction:
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; CHECK-FIXME: fneg {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
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; CHECK-FIXME: fmla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
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entry:
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%mul = mul <8 x i16> %c, %b
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%m = bitcast <8 x i16> %mul to <8 x half>
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%sub = fsub fast <8 x half> %m, %a
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ret <8 x half> %sub
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}
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define <8 x half> @test_FMLSv8i16_indexed_OP2(<8 x half> %a, <8 x i16> %b, <8 x i16> %c) {
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; CHECK-LABEL: test_FMLSv8i16_indexed_OP2:
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; CHECK-FIXME: Currently LLVM produces inefficient code:
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; CHECK: mul
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; CHECK: fsub
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; CHECK-FIXME: It should instead produce the following instruction:
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; CHECK-FIXME: fmls {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
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entry:
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%mul = mul <8 x i16> %c, %b
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%m = bitcast <8 x i16> %mul to <8 x half>
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%sub = fsub fast <8 x half> %a, %m
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ret <8 x half> %sub
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}
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