329 lines
9.2 KiB
Plaintext
329 lines
9.2 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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#
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# Test that we can select G_TRN1 and G_TRN2.
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#
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# Each testcase is named based off of the instruction which should be selected.
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...
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---
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name: TRN1v2i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1
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; CHECK-LABEL: name: TRN1v2i32
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[TRN1v2i32_:%[0-9]+]]:fpr64 = TRN1v2i32 [[COPY]], [[COPY1]]
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; CHECK: $d0 = COPY [[TRN1v2i32_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<2 x s32>) = COPY $d0
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%1:fpr(<2 x s32>) = COPY $d1
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%2:fpr(<2 x s32>) = G_TRN1 %0, %1
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$d0 = COPY %2(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: TRN1v2i64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: TRN1v2i64
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[TRN1v2i64_:%[0-9]+]]:fpr128 = TRN1v2i64 [[COPY]], [[COPY1]]
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; CHECK: $q0 = COPY [[TRN1v2i64_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<2 x s64>) = COPY $q0
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%1:fpr(<2 x s64>) = COPY $q1
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%2:fpr(<2 x s64>) = G_TRN1 %0, %1
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$q0 = COPY %2(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: TRN1v4i16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1
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; CHECK-LABEL: name: TRN1v4i16
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[TRN1v4i16_:%[0-9]+]]:fpr64 = TRN1v4i16 [[COPY]], [[COPY1]]
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; CHECK: $d0 = COPY [[TRN1v4i16_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<4 x s16>) = COPY $d0
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%1:fpr(<4 x s16>) = COPY $d1
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%2:fpr(<4 x s16>) = G_TRN1 %0, %1
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$d0 = COPY %2(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: TRN1v4i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: TRN1v4i32
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[TRN1v4i32_:%[0-9]+]]:fpr128 = TRN1v4i32 [[COPY]], [[COPY1]]
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; CHECK: $q0 = COPY [[TRN1v4i32_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s32>) = COPY $q0
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%1:fpr(<4 x s32>) = COPY $q1
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%2:fpr(<4 x s32>) = G_TRN1 %0, %1
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: TRN1v8i8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1
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; CHECK-LABEL: name: TRN1v8i8
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[TRN1v8i8_:%[0-9]+]]:fpr64 = TRN1v8i8 [[COPY]], [[COPY1]]
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; CHECK: $d0 = COPY [[TRN1v8i8_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<8 x s8>) = COPY $d0
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%1:fpr(<8 x s8>) = COPY $d1
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%2:fpr(<8 x s8>) = G_TRN1 %0, %1
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$d0 = COPY %2(<8 x s8>)
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RET_ReallyLR implicit $d0
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...
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---
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name: TRN1v8i16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: TRN1v8i16
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[TRN1v8i16_:%[0-9]+]]:fpr128 = TRN1v8i16 [[COPY]], [[COPY1]]
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; CHECK: $q0 = COPY [[TRN1v8i16_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<8 x s16>) = COPY $q0
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%1:fpr(<8 x s16>) = COPY $q1
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%2:fpr(<8 x s16>) = G_TRN1 %0, %1
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$q0 = COPY %2(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: TRN1v16i8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: TRN1v16i8
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[TRN1v16i8_:%[0-9]+]]:fpr128 = TRN1v16i8 [[COPY]], [[COPY1]]
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; CHECK: $q0 = COPY [[TRN1v16i8_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<16 x s8>) = COPY $q0
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%1:fpr(<16 x s8>) = COPY $q1
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%2:fpr(<16 x s8>) = G_TRN1 %0, %1
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$q0 = COPY %2(<16 x s8>)
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RET_ReallyLR implicit $q0
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...
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---
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name: TRN2v2i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1
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; CHECK-LABEL: name: TRN2v2i32
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[TRN2v2i32_:%[0-9]+]]:fpr64 = TRN2v2i32 [[COPY]], [[COPY1]]
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; CHECK: $d0 = COPY [[TRN2v2i32_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<2 x s32>) = COPY $d0
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%1:fpr(<2 x s32>) = COPY $d1
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%2:fpr(<2 x s32>) = G_TRN2 %0, %1
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$d0 = COPY %2(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: TRN2v2i64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: TRN2v2i64
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[TRN2v2i64_:%[0-9]+]]:fpr128 = TRN2v2i64 [[COPY]], [[COPY1]]
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; CHECK: $q0 = COPY [[TRN2v2i64_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<2 x s64>) = COPY $q0
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%1:fpr(<2 x s64>) = COPY $q1
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%2:fpr(<2 x s64>) = G_TRN2 %0, %1
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$q0 = COPY %2(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: TRN2v4i16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1
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; CHECK-LABEL: name: TRN2v4i16
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[TRN2v4i16_:%[0-9]+]]:fpr64 = TRN2v4i16 [[COPY]], [[COPY1]]
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; CHECK: $d0 = COPY [[TRN2v4i16_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<4 x s16>) = COPY $d0
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%1:fpr(<4 x s16>) = COPY $d1
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%2:fpr(<4 x s16>) = G_TRN2 %0, %1
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$d0 = COPY %2(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: TRN2v4i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: TRN2v4i32
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[TRN2v4i32_:%[0-9]+]]:fpr128 = TRN2v4i32 [[COPY]], [[COPY1]]
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; CHECK: $q0 = COPY [[TRN2v4i32_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s32>) = COPY $q0
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%1:fpr(<4 x s32>) = COPY $q1
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%2:fpr(<4 x s32>) = G_TRN2 %0, %1
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: TRN2v8i8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1
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; CHECK-LABEL: name: TRN2v8i8
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[TRN2v8i8_:%[0-9]+]]:fpr64 = TRN2v8i8 [[COPY]], [[COPY1]]
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; CHECK: $d0 = COPY [[TRN2v8i8_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<8 x s8>) = COPY $d0
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%1:fpr(<8 x s8>) = COPY $d1
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%2:fpr(<8 x s8>) = G_TRN2 %0, %1
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$d0 = COPY %2(<8 x s8>)
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RET_ReallyLR implicit $d0
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...
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---
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name: TRN2v8i16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: TRN2v8i16
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[TRN2v8i16_:%[0-9]+]]:fpr128 = TRN2v8i16 [[COPY]], [[COPY1]]
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; CHECK: $q0 = COPY [[TRN2v8i16_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<8 x s16>) = COPY $q0
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%1:fpr(<8 x s16>) = COPY $q1
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%2:fpr(<8 x s16>) = G_TRN2 %0, %1
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$q0 = COPY %2(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: TRN2v16i8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: TRN2v16i8
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[TRN2v16i8_:%[0-9]+]]:fpr128 = TRN2v16i8 [[COPY]], [[COPY1]]
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; CHECK: $q0 = COPY [[TRN2v16i8_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<16 x s8>) = COPY $q0
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%1:fpr(<16 x s8>) = COPY $q1
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%2:fpr(<16 x s8>) = G_TRN2 %0, %1
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$q0 = COPY %2(<16 x s8>)
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RET_ReallyLR implicit $q0
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