122 lines
4.2 KiB
Plaintext
122 lines
4.2 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define i32 @test_store_release_i64(i32 %a, i64* %addr) {
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ret i32 %a
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}
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define i32 @test_store_release_i32(i32 %a, i64* %addr) {
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ret i32 %a
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}
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define void @test_store_release_i8(i32, i8 %val, i8* %addr) { ret void }
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define void @test_store_release_i16(i32, i16 %val, i16* %addr) { ret void }
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...
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---
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name: test_store_release_i64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $x1, $x2
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; CHECK-LABEL: name: test_store_release_i64
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; CHECK: liveins: $w0, $x1, $x2
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
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; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
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; CHECK: early-clobber %2:gpr32 = STLXRX [[COPY]], [[COPY1]] :: (volatile store 8 into %ir.addr)
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; CHECK: $w0 = COPY %2
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; CHECK: RET_ReallyLR implicit $w0
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%1:gpr(s64) = COPY $x1
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%2:gpr(p0) = COPY $x2
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%3:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %1(s64), %2(p0) :: (volatile store 8 into %ir.addr)
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$w0 = COPY %3(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: test_store_release_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1, $x2
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; CHECK-LABEL: name: test_store_release_i32
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; CHECK: liveins: $w0, $w1, $x2
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
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; CHECK: early-clobber %3:gpr32 = STLXRW [[COPY]], [[COPY1]] :: (volatile store 4 into %ir.addr)
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; CHECK: $w0 = COPY %3
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; CHECK: RET_ReallyLR implicit $w0
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%1:gpr(s32) = COPY $w1
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%2:gpr(p0) = COPY $x2
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%3:gpr(s64) = G_ZEXT %1(s32)
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%4:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %3(s64), %2(p0) :: (volatile store 4 into %ir.addr)
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$w0 = COPY %4(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: test_store_release_i8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1, $x2
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; CHECK-LABEL: name: test_store_release_i8
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; CHECK: liveins: $w0, $w1, $x2
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
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; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
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; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
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; CHECK: early-clobber %5:gpr32 = STLXRB [[COPY2]], [[COPY1]] :: (volatile store 1 into %ir.addr)
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; CHECK: $w0 = COPY %5
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; CHECK: RET_ReallyLR implicit $w0
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%3:gpr(s32) = COPY $w1
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%2:gpr(p0) = COPY $x2
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%6:gpr(s64) = G_CONSTANT i64 255
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%7:gpr(s64) = G_ANYEXT %3(s32)
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%4:gpr(s64) = G_AND %7, %6
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%5:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %4(s64), %2(p0) :: (volatile store 1 into %ir.addr)
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: test_store_release_i16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1, $x2
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; CHECK-LABEL: name: test_store_release_i16
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; CHECK: liveins: $w0, $w1, $x2
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
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; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
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; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
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; CHECK: early-clobber %5:gpr32 = STLXRH [[COPY2]], [[COPY1]] :: (volatile store 2 into %ir.addr)
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; CHECK: $w0 = COPY %5
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; CHECK: RET_ReallyLR implicit $w0
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%3:gpr(s32) = COPY $w1
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%2:gpr(p0) = COPY $x2
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%6:gpr(s64) = G_CONSTANT i64 65535
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%7:gpr(s64) = G_ANYEXT %3(s32)
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%4:gpr(s64) = G_AND %7, %6
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%5:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %4(s64), %2(p0) :: (volatile store 2 into %ir.addr)
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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