124 lines
3.5 KiB
Plaintext
124 lines
3.5 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: logical_imm_64_and
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: logical_imm_64_and
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 4096
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; CHECK: $x0 = COPY [[ANDXri]]
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; CHECK: RET_ReallyLR implicit $x0
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%0:gpr(s64) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 1
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%2:gpr(s64) = G_AND %0, %1:gpr(s64)
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$x0 = COPY %2:gpr(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: logical_imm_64_or
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: logical_imm_64_or
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[ORRXri:%[0-9]+]]:gpr64sp = ORRXri [[COPY]], 4096
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; CHECK: $x0 = COPY [[ORRXri]]
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; CHECK: RET_ReallyLR implicit $x0
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%0:gpr(s64) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 1
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%2:gpr(s64) = G_OR %0, %1:gpr(s64)
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$x0 = COPY %2:gpr(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: logical_imm_64_xor
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: logical_imm_64_xor
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[EORXri:%[0-9]+]]:gpr64sp = EORXri [[COPY]], 4096
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; CHECK: $x0 = COPY [[EORXri]]
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; CHECK: RET_ReallyLR implicit $x0
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%0:gpr(s64) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 1
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%2:gpr(s64) = G_XOR %0, %1:gpr(s64)
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$x0 = COPY %2:gpr(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: logical_imm_32_and
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: logical_imm_32_and
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; CHECK: liveins: $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[ANDWri:%[0-9]+]]:gpr32sp = ANDWri [[COPY]], 0
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; CHECK: $w0 = COPY [[ANDWri]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_AND %0, %1:gpr(s32)
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$w0 = COPY %2:gpr(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: logical_imm_32_or
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: logical_imm_32_or
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; CHECK: liveins: $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[ORRWri:%[0-9]+]]:gpr32sp = ORRWri [[COPY]], 0
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; CHECK: $w0 = COPY [[ORRWri]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_OR %0, %1:gpr(s32)
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$w0 = COPY %2:gpr(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: logical_imm_32_xor
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: logical_imm_32_xor
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; CHECK: liveins: $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[EORWri:%[0-9]+]]:gpr32sp = EORWri [[COPY]], 0
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; CHECK: $w0 = COPY [[EORWri]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_XOR %0, %1:gpr(s32)
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$w0 = COPY %2:gpr(s32)
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RET_ReallyLR implicit $w0
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...
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