199 lines
5.1 KiB
Plaintext
199 lines
5.1 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -mattr=+fullfp16 -o - | FileCheck %s
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...
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---
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name: test_f64.intrinsic_round
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_f64.intrinsic_round
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[FRINTADr:%[0-9]+]]:fpr64 = FRINTADr [[COPY]]
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; CHECK: $d0 = COPY [[FRINTADr]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(s64) = COPY $d0
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%1:fpr(s64) = G_INTRINSIC_ROUND %0
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$d0 = COPY %1(s64)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_f32.intrinsic_round
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $s0
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; CHECK-LABEL: name: test_f32.intrinsic_round
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; CHECK: liveins: $s0
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[FRINTASr:%[0-9]+]]:fpr32 = FRINTASr [[COPY]]
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; CHECK: $s0 = COPY [[FRINTASr]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:fpr(s32) = COPY $s0
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%1:fpr(s32) = G_INTRINSIC_ROUND %0
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$s0 = COPY %1(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: test_f16.intrinsic_round
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $h0
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; CHECK-LABEL: name: test_f16.intrinsic_round
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; CHECK: liveins: $h0
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; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
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; CHECK: [[FRINTAHr:%[0-9]+]]:fpr16 = FRINTAHr [[COPY]]
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; CHECK: $h0 = COPY [[FRINTAHr]]
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; CHECK: RET_ReallyLR implicit $h0
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%0:fpr(s16) = COPY $h0
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%1:fpr(s16) = G_INTRINSIC_ROUND %0
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$h0 = COPY %1(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: test_v4f16.intrinsic_round
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_v4f16.intrinsic_round
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[FRINTAv4f16_:%[0-9]+]]:fpr64 = FRINTAv4f16 [[COPY]]
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; CHECK: $d0 = COPY [[FRINTAv4f16_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<4 x s16>) = COPY $d0
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%1:fpr(<4 x s16>) = G_INTRINSIC_ROUND %0
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$d0 = COPY %1(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v8f16.intrinsic_round
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v8f16.intrinsic_round
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[FRINTAv8f16_:%[0-9]+]]:fpr128 = FRINTAv8f16 [[COPY]]
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; CHECK: $q0 = COPY [[FRINTAv8f16_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<8 x s16>) = COPY $q0
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%1:fpr(<8 x s16>) = G_INTRINSIC_ROUND %0
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v2f32.intrinsic_round
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_v2f32.intrinsic_round
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[FRINTAv2f32_:%[0-9]+]]:fpr64 = FRINTAv2f32 [[COPY]]
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; CHECK: $d0 = COPY [[FRINTAv2f32_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<2 x s32>) = COPY $d0
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%1:fpr(<2 x s32>) = G_INTRINSIC_ROUND %0
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$d0 = COPY %1(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v4f32.intrinsic_round
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v4f32.intrinsic_round
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[FRINTAv4f32_:%[0-9]+]]:fpr128 = FRINTAv4f32 [[COPY]]
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; CHECK: $q0 = COPY [[FRINTAv4f32_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s32>) = COPY $q0
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%1:fpr(<4 x s32>) = G_INTRINSIC_ROUND %0
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$q0 = COPY %1(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v2f64.intrinsic_round
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v2f64.intrinsic_round
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[FRINTAv2f64_:%[0-9]+]]:fpr128 = FRINTAv2f64 [[COPY]]
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; CHECK: $q0 = COPY [[FRINTAv2f64_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<2 x s64>) = COPY $q0
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%1:fpr(<2 x s64>) = G_INTRINSIC_ROUND %0
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$q0 = COPY %1(<2 x s64>)
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RET_ReallyLR implicit $q0
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