638 lines
14 KiB
Plaintext
638 lines
14 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: fptrunc_s16_s32_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $s0
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; CHECK-LABEL: name: fptrunc_s16_s32_fpr
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
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; CHECK: $h0 = COPY [[FCVTHSr]]
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%0(s32) = COPY $s0
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%1(s16) = G_FPTRUNC %0
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$h0 = COPY %1(s16)
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...
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---
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name: fptrunc_s16_s64_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: fptrunc_s16_s64_fpr
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[FCVTHDr:%[0-9]+]]:fpr16 = FCVTHDr [[COPY]]
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; CHECK: $h0 = COPY [[FCVTHDr]]
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%0(s64) = COPY $d0
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%1(s16) = G_FPTRUNC %0
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$h0 = COPY %1(s16)
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...
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---
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name: fptrunc_s32_s64_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: fptrunc_s32_s64_fpr
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[FCVTSDr:%[0-9]+]]:fpr32 = FCVTSDr [[COPY]]
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; CHECK: $s0 = COPY [[FCVTSDr]]
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%0(s64) = COPY $d0
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%1(s32) = G_FPTRUNC %0
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$s0 = COPY %1(s32)
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...
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---
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name: fptrunc_v4s16_v4s32_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: fptrunc_v4s16_v4s32_fpr
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[FCVTNv4i16:%[0-9]+]]:fpr64 = FCVTNv4i16 [[COPY]]
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; CHECK: $d0 = COPY [[FCVTNv4i16]]
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%0(<4 x s32>) = COPY $q0
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%1(<4 x s16>) = G_FPTRUNC %0
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$d0 = COPY %1(<4 x s16>)
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...
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---
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name: fptrunc_v2s32_v2s64_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: fptrunc_v2s32_v2s64_fpr
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[FCVTNv2i32:%[0-9]+]]:fpr64 = FCVTNv2i32 [[COPY]]
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; CHECK: $d0 = COPY [[FCVTNv2i32]]
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%0(<2 x s64>) = COPY $q0
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%1(<2 x s32>) = G_FPTRUNC %0
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$d0 = COPY %1(<2 x s32>)
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...
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---
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name: fpext_s32_s16_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $h0
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; CHECK-LABEL: name: fpext_s32_s16_fpr
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; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
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; CHECK: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY]]
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; CHECK: $s0 = COPY [[FCVTSHr]]
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%0(s16) = COPY $h0
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%1(s32) = G_FPEXT %0
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$s0 = COPY %1(s32)
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...
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---
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name: fpext_s64_s16_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $h0
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; CHECK-LABEL: name: fpext_s64_s16_fpr
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; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
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; CHECK: [[FCVTDHr:%[0-9]+]]:fpr64 = FCVTDHr [[COPY]]
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; CHECK: $d0 = COPY [[FCVTDHr]]
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%0(s16) = COPY $h0
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%1(s64) = G_FPEXT %0
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$d0 = COPY %1(s64)
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...
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---
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name: fpext_s64_s32_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: fpext_s64_s32_fpr
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[FCVTDSr:%[0-9]+]]:fpr64 = FCVTDSr [[COPY]]
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; CHECK: $d0 = COPY [[FCVTDSr]]
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%0(s32) = COPY $s0
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%1(s64) = G_FPEXT %0
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$d0 = COPY %1(s64)
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...
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---
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name: fpext_v4s32_v4s16_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: fpext_v4s32_v4s16_fpr
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[FCVTLv4i16:%[0-9]+]]:fpr128 = FCVTLv4i16 [[COPY]]
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; CHECK: $q0 = COPY [[FCVTLv4i16]]
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%0(<4 x s16>) = COPY $d0
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%1(<4 x s32>) = G_FPEXT %0
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$q0 = COPY %1(<4 x s32>)
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...
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---
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name: fpext_v2s64_v2s32_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: fpext_v2s64_v2s32_fpr
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[FCVTLv2i32:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
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; CHECK: $q0 = COPY [[FCVTLv2i32]]
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%0(<2 x s32>) = COPY $d0
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%1(<2 x s64>) = G_FPEXT %0
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$q0 = COPY %1(<2 x s64>)
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...
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---
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name: sitofp_s32_s32_fpr_gpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: sitofp_s32_s32_fpr_gpr
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[SCVTFUWSri:%[0-9]+]]:fpr32 = SCVTFUWSri [[COPY]]
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; CHECK: $s0 = COPY [[SCVTFUWSri]]
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%0(s32) = COPY $w0
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%1(s32) = G_SITOFP %0
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$s0 = COPY %1(s32)
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...
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---
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name: sitofp_s32_s32_fpr_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $s0
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; CHECK-LABEL: name: sitofp_s32_s32_fpr_fpr
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[SCVTFv1i32:%[0-9]+]]:fpr32 = SCVTFv1i32 [[COPY]]
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; CHECK: $s0 = COPY [[SCVTFv1i32]]
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%0(s32) = COPY $s0
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%1(s32) = G_SITOFP %0
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$s0 = COPY %1(s32)
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...
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---
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name: uitofp_s32_s32_fpr_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $s0
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; CHECK-LABEL: name: uitofp_s32_s32_fpr_fpr
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[UCVTFv1i32:%[0-9]+]]:fpr32 = UCVTFv1i32 [[COPY]]
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; CHECK: $s0 = COPY [[UCVTFv1i32]]
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%0(s32) = COPY $s0
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%1(s32) = G_UITOFP %0
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$s0 = COPY %1(s32)
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...
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---
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name: sitofp_s32_s64_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: sitofp_s32_s64_fpr
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[SCVTFUXSri:%[0-9]+]]:fpr32 = SCVTFUXSri [[COPY]]
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; CHECK: $s0 = COPY [[SCVTFUXSri]]
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%0(s64) = COPY $x0
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%1(s32) = G_SITOFP %0
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$s0 = COPY %1(s32)
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...
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---
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name: sitofp_s64_s32_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: sitofp_s64_s32_fpr
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[SCVTFUWDri:%[0-9]+]]:fpr64 = SCVTFUWDri [[COPY]]
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; CHECK: $d0 = COPY [[SCVTFUWDri]]
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%0(s32) = COPY $w0
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%1(s64) = G_SITOFP %0
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$d0 = COPY %1(s64)
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...
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---
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name: sitofp_s64_s32_fpr_both
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $s0
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; CHECK-LABEL: name: sitofp_s64_s32_fpr
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY]]
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; CHECK: [[SCVTFUWDri:%[0-9]+]]:fpr64 = SCVTFUWDri [[COPY2]]
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; CHECK: $d0 = COPY [[SCVTFUWDri]]
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%0(s32) = COPY $s0
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%1(s64) = G_SITOFP %0
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$d0 = COPY %1(s64)
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...
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---
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name: sitofp_s64_s64_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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|
|
- { id: 1, class: fpr }
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $x0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: sitofp_s64_s64_fpr
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
||
|
|
; CHECK: [[SCVTFUXDri:%[0-9]+]]:fpr64 = SCVTFUXDri [[COPY]]
|
||
|
|
; CHECK: $d0 = COPY [[SCVTFUXDri]]
|
||
|
|
%0(s64) = COPY $x0
|
||
|
|
%1(s64) = G_SITOFP %0
|
||
|
|
$d0 = COPY %1(s64)
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: uitofp_s32_s32_fpr
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
registers:
|
||
|
|
- { id: 0, class: gpr }
|
||
|
|
- { id: 1, class: fpr }
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $w0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: uitofp_s32_s32_fpr
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
||
|
|
; CHECK: [[UCVTFUWSri:%[0-9]+]]:fpr32 = UCVTFUWSri [[COPY]]
|
||
|
|
; CHECK: $s0 = COPY [[UCVTFUWSri]]
|
||
|
|
%0(s32) = COPY $w0
|
||
|
|
%1(s32) = G_UITOFP %0
|
||
|
|
$s0 = COPY %1(s32)
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: uitofp_s32_s64_fpr
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
registers:
|
||
|
|
- { id: 0, class: gpr }
|
||
|
|
- { id: 1, class: fpr }
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $x0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: uitofp_s32_s64_fpr
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
||
|
|
; CHECK: [[UCVTFUXSri:%[0-9]+]]:fpr32 = UCVTFUXSri [[COPY]]
|
||
|
|
; CHECK: $s0 = COPY [[UCVTFUXSri]]
|
||
|
|
%0(s64) = COPY $x0
|
||
|
|
%1(s32) = G_UITOFP %0
|
||
|
|
$s0 = COPY %1(s32)
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: uitofp_s64_s32_fpr
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
registers:
|
||
|
|
- { id: 0, class: gpr }
|
||
|
|
- { id: 1, class: fpr }
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $w0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: uitofp_s64_s32_fpr
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
||
|
|
; CHECK: [[UCVTFUWDri:%[0-9]+]]:fpr64 = UCVTFUWDri [[COPY]]
|
||
|
|
; CHECK: $d0 = COPY [[UCVTFUWDri]]
|
||
|
|
%0(s32) = COPY $w0
|
||
|
|
%1(s64) = G_UITOFP %0
|
||
|
|
$d0 = COPY %1(s64)
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: uitofp_s64_s64_fpr
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
registers:
|
||
|
|
- { id: 0, class: gpr }
|
||
|
|
- { id: 1, class: fpr }
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $x0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: uitofp_s64_s64_fpr
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
||
|
|
; CHECK: [[UCVTFUXDri:%[0-9]+]]:fpr64 = UCVTFUXDri [[COPY]]
|
||
|
|
; CHECK: $d0 = COPY [[UCVTFUXDri]]
|
||
|
|
%0(s64) = COPY $x0
|
||
|
|
%1(s64) = G_UITOFP %0
|
||
|
|
$d0 = COPY %1(s64)
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: fptosi_s32_s32_gpr
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
registers:
|
||
|
|
- { id: 0, class: fpr }
|
||
|
|
- { id: 1, class: gpr }
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $s0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: fptosi_s32_s32_gpr
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
|
||
|
|
; CHECK: [[FCVTZSUWSr:%[0-9]+]]:gpr32 = FCVTZSUWSr [[COPY]]
|
||
|
|
; CHECK: $w0 = COPY [[FCVTZSUWSr]]
|
||
|
|
%0(s32) = COPY $s0
|
||
|
|
%1(s32) = G_FPTOSI %0
|
||
|
|
$w0 = COPY %1(s32)
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: fptosi_s32_s64_gpr
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
registers:
|
||
|
|
- { id: 0, class: fpr }
|
||
|
|
- { id: 1, class: gpr }
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $d0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: fptosi_s32_s64_gpr
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
||
|
|
; CHECK: [[FCVTZSUWDr:%[0-9]+]]:gpr32 = FCVTZSUWDr [[COPY]]
|
||
|
|
; CHECK: $w0 = COPY [[FCVTZSUWDr]]
|
||
|
|
%0(s64) = COPY $d0
|
||
|
|
%1(s32) = G_FPTOSI %0
|
||
|
|
$w0 = COPY %1(s32)
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: fptosi_s64_s32_gpr
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
registers:
|
||
|
|
- { id: 0, class: fpr }
|
||
|
|
- { id: 1, class: gpr }
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $s0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: fptosi_s64_s32_gpr
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
|
||
|
|
; CHECK: [[FCVTZSUXSr:%[0-9]+]]:gpr64 = FCVTZSUXSr [[COPY]]
|
||
|
|
; CHECK: $x0 = COPY [[FCVTZSUXSr]]
|
||
|
|
%0(s32) = COPY $s0
|
||
|
|
%1(s64) = G_FPTOSI %0
|
||
|
|
$x0 = COPY %1(s64)
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: fptosi_s64_s64_gpr
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
registers:
|
||
|
|
- { id: 0, class: fpr }
|
||
|
|
- { id: 1, class: gpr }
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $d0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: fptosi_s64_s64_gpr
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
||
|
|
; CHECK: [[FCVTZSUXDr:%[0-9]+]]:gpr64 = FCVTZSUXDr [[COPY]]
|
||
|
|
; CHECK: $x0 = COPY [[FCVTZSUXDr]]
|
||
|
|
%0(s64) = COPY $d0
|
||
|
|
%1(s64) = G_FPTOSI %0
|
||
|
|
$x0 = COPY %1(s64)
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: fptoui_s32_s32_gpr
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
registers:
|
||
|
|
- { id: 0, class: fpr }
|
||
|
|
- { id: 1, class: gpr }
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $s0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: fptoui_s32_s32_gpr
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
|
||
|
|
; CHECK: [[FCVTZUUWSr:%[0-9]+]]:gpr32 = FCVTZUUWSr [[COPY]]
|
||
|
|
; CHECK: $w0 = COPY [[FCVTZUUWSr]]
|
||
|
|
%0(s32) = COPY $s0
|
||
|
|
%1(s32) = G_FPTOUI %0
|
||
|
|
$w0 = COPY %1(s32)
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: fptoui_s32_s64_gpr
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
registers:
|
||
|
|
- { id: 0, class: fpr }
|
||
|
|
- { id: 1, class: gpr }
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $d0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: fptoui_s32_s64_gpr
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
||
|
|
; CHECK: [[FCVTZUUWDr:%[0-9]+]]:gpr32 = FCVTZUUWDr [[COPY]]
|
||
|
|
; CHECK: $w0 = COPY [[FCVTZUUWDr]]
|
||
|
|
%0(s64) = COPY $d0
|
||
|
|
%1(s32) = G_FPTOUI %0
|
||
|
|
$w0 = COPY %1(s32)
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: fptoui_s64_s32_gpr
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
registers:
|
||
|
|
- { id: 0, class: fpr }
|
||
|
|
- { id: 1, class: gpr }
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $s0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: fptoui_s64_s32_gpr
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
|
||
|
|
; CHECK: [[FCVTZUUXSr:%[0-9]+]]:gpr64 = FCVTZUUXSr [[COPY]]
|
||
|
|
; CHECK: $x0 = COPY [[FCVTZUUXSr]]
|
||
|
|
%0(s32) = COPY $s0
|
||
|
|
%1(s64) = G_FPTOUI %0
|
||
|
|
$x0 = COPY %1(s64)
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: fptoui_s64_s64_gpr
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
registers:
|
||
|
|
- { id: 0, class: fpr }
|
||
|
|
- { id: 1, class: gpr }
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $d0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: fptoui_s64_s64_gpr
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
||
|
|
; CHECK: [[FCVTZUUXDr:%[0-9]+]]:gpr64 = FCVTZUUXDr [[COPY]]
|
||
|
|
; CHECK: $x0 = COPY [[FCVTZUUXDr]]
|
||
|
|
%0(s64) = COPY $d0
|
||
|
|
%1(s64) = G_FPTOUI %0
|
||
|
|
$x0 = COPY %1(s64)
|
||
|
|
...
|