49 lines
1.4 KiB
Plaintext
49 lines
1.4 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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define void @aextload_s32_from_s16(i16 *%addr) { ret void }
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define void @aextload_s32_from_s16_not_combined(i16 *%addr) { ret void }
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...
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---
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name: aextload_s32_from_s16
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: aextload_s32_from_s16
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr)
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; CHECK: $w0 = COPY [[T0]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_LOAD %0 :: (load 2 from %ir.addr)
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$w0 = COPY %1(s32)
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...
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---
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name: aextload_s32_from_s16_not_combined
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: aextload_s32_from_s16
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr)
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; CHECK: [[T1:%[0-9]+]]:gpr32all = COPY [[T0]]
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; CHECK: $w0 = COPY [[T1]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
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%2:gpr(s32) = G_ANYEXT %1
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$w0 = COPY %2(s32)
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...
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