154 lines
3.8 KiB
Plaintext
154 lines
3.8 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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#
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# Test G_EXT selection using AArch64ext patterns.
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...
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---
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name: v8s8_EXTv8i8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1
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; CHECK-LABEL: name: v8s8_EXTv8i8
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; CHECK: liveins: $d0, $d1
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; CHECK: %v1:fpr64 = COPY $d0
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; CHECK: %v2:fpr64 = COPY $d1
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; CHECK: %shuf:fpr64 = EXTv8i8 %v1, %v2, 3
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%v1:fpr(<8 x s8>) = COPY $d0
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%v2:fpr(<8 x s8>) = COPY $d1
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%3:gpr(s32) = G_CONSTANT i32 3
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%shuf:fpr(<8 x s8>) = G_EXT %v1, %v2, %3(s32)
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...
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---
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name: v16s8_EXTv16i8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: v16s8_EXTv16i8
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; CHECK: liveins: $q0, $q1
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; CHECK: %v1:fpr128 = COPY $q0
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; CHECK: %v2:fpr128 = COPY $q1
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; CHECK: %shuf:fpr128 = EXTv16i8 %v1, %v2, 3
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%v1:fpr(<16 x s8>) = COPY $q0
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%v2:fpr(<16 x s8>) = COPY $q1
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%3:gpr(s32) = G_CONSTANT i32 3
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%shuf:fpr(<16 x s8>) = G_EXT %v1, %v2, %3(s32)
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...
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---
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name: v4s16_EXTv8i8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1
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; CHECK-LABEL: name: v4s16_EXTv8i8
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; CHECK: liveins: $d0, $d1
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; CHECK: %v1:fpr64 = COPY $d0
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; CHECK: %v2:fpr64 = COPY $d1
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; CHECK: %shuf:fpr64 = EXTv8i8 %v1, %v2, 6
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%v1:fpr(<4 x s16>) = COPY $d0
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%v2:fpr(<4 x s16>) = COPY $d1
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%3:gpr(s32) = G_CONSTANT i32 6
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%shuf:fpr(<4 x s16>) = G_EXT %v1, %v2, %3(s32)
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...
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---
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name: v8s16_EXTv16i8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: v8s16_EXTv16i8
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; CHECK: liveins: $q0, $q1
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; CHECK: %v1:fpr128 = COPY $q0
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; CHECK: %v2:fpr128 = COPY $q1
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; CHECK: %shuf:fpr128 = EXTv16i8 %v2, %v1, 10
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%v1:fpr(<8 x s16>) = COPY $q0
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%v2:fpr(<8 x s16>) = COPY $q1
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%3:gpr(s32) = G_CONSTANT i32 10
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%shuf:fpr(<8 x s16>) = G_EXT %v2, %v1, %3(s32)
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...
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...
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---
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name: v4s32_EXTv16i8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: v4s32_EXTv16i8
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; CHECK: liveins: $q0, $q1
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; CHECK: %v1:fpr128 = COPY $q0
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; CHECK: %v2:fpr128 = COPY $q1
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; CHECK: %shuf:fpr128 = EXTv16i8 %v1, %v2, 12
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%v1:fpr(<4 x s32>) = COPY $q0
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%v2:fpr(<4 x s32>) = COPY $q1
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%3:gpr(s32) = G_CONSTANT i32 12
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%shuf:fpr(<4 x s32>) = G_EXT %v1, %v2, %3(s32)
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...
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---
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name: v2s32_EXTv8i8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1
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; CHECK-LABEL: name: v2s32_EXTv8i8
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; CHECK: liveins: $d0, $d1
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; CHECK: %v1:fpr64 = COPY $d0
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; CHECK: %v2:fpr64 = COPY $d1
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; CHECK: %shuf:fpr64 = EXTv8i8 %v1, %v2, 2
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%v1:fpr(<2 x s32>) = COPY $d0
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%v2:fpr(<2 x s32>) = COPY $d1
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%3:gpr(s32) = G_CONSTANT i32 2
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%shuf:fpr(<2 x s32>) = G_EXT %v1, %v2, %3(s32)
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...
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---
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name: v2s64_EXTv16i8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: v2s64_EXTv16i8
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; CHECK: liveins: $q0, $q1
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; CHECK: %v1:fpr128 = COPY $q0
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; CHECK: %v2:fpr128 = COPY $q1
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; CHECK: %shuf:fpr128 = EXTv16i8 %v1, %v2, 2
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%v1:fpr(<2 x s64>) = COPY $q0
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%v2:fpr(<2 x s64>) = COPY $q1
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%3:gpr(s32) = G_CONSTANT i32 2
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%shuf:fpr(<2 x s64>) = G_EXT %v1, %v2, %3(s32)
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...
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