338 lines
9.0 KiB
Plaintext
338 lines
9.0 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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#
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# GPR variants should not use INSERT_SUBREG. FPR variants (DUP<ty>lane) should.
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...
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---
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name: DUPv4i32gpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0
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; CHECK-LABEL: name: DUPv4i32gpr
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; CHECK: liveins: $w0
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; CHECK: %copy:gpr32 = COPY $w0
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; CHECK: %dup:fpr128 = DUPv4i32gpr %copy
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; CHECK: $q0 = COPY %dup
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; CHECK: RET_ReallyLR implicit $q0
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%copy:gpr(s32) = COPY $w0
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%dup:fpr(<4 x s32>) = G_DUP %copy(s32)
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$q0 = COPY %dup(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: DUPv2i64gpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: DUPv2i64gpr
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; CHECK: liveins: $x0
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; CHECK: %copy:gpr64 = COPY $x0
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; CHECK: %dup:fpr128 = DUPv2i64gpr %copy
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; CHECK: $q0 = COPY %dup
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; CHECK: RET_ReallyLR implicit $q0
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%copy:gpr(s64) = COPY $x0
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%dup:fpr(<2 x s64>) = G_DUP %copy(s64)
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$q0 = COPY %dup(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: DUPv2i32gpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0
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; CHECK-LABEL: name: DUPv2i32gpr
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; CHECK: liveins: $w0
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; CHECK: %copy:gpr32 = COPY $w0
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; CHECK: %dup:fpr64 = DUPv2i32gpr %copy
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; CHECK: $d0 = COPY %dup
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; CHECK: RET_ReallyLR implicit $d0
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%copy:gpr(s32) = COPY $w0
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%dup:fpr(<2 x s32>) = G_DUP %copy(s32)
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$d0 = COPY %dup(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: DUPv4i32lane
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $s0
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; CHECK-LABEL: name: DUPv4i32lane
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; CHECK: liveins: $s0
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; CHECK: %copy:fpr32 = COPY $s0
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.ssub
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; CHECK: %dup:fpr128 = DUPv4i32lane [[INSERT_SUBREG]], 0
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; CHECK: $q0 = COPY %dup
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; CHECK: RET_ReallyLR implicit $q0
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%copy:fpr(s32) = COPY $s0
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%dup:fpr(<4 x s32>) = G_DUP %copy(s32)
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$q0 = COPY %dup(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: DUPv2i64lane
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $d0
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; CHECK-LABEL: name: DUPv2i64lane
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; CHECK: liveins: $d0
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; CHECK: %copy:fpr64 = COPY $d0
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.dsub
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; CHECK: %dup:fpr128 = DUPv2i64lane [[INSERT_SUBREG]], 0
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; CHECK: $q0 = COPY %dup
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; CHECK: RET_ReallyLR implicit $q0
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%copy:fpr(s64) = COPY $d0
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%dup:fpr(<2 x s64>) = G_DUP %copy(s64)
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$q0 = COPY %dup(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: DUPv2i32lane
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $s0
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; CHECK-LABEL: name: DUPv2i32lane
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; CHECK: liveins: $s0
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; CHECK: %copy:fpr32 = COPY $s0
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.ssub
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; CHECK: %dup:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
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; CHECK: $d0 = COPY %dup
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; CHECK: RET_ReallyLR implicit $d0
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%copy:fpr(s32) = COPY $s0
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%dup:fpr(<2 x s32>) = G_DUP %copy(s32)
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$d0 = COPY %dup(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: DUPv4i16lane
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $h0
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; CHECK-LABEL: name: DUPv4i16lane
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; CHECK: liveins: $h0
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; CHECK: %copy:fpr16 = COPY $h0
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.hsub
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; CHECK: %dup:fpr64 = DUPv4i16lane [[INSERT_SUBREG]], 0
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; CHECK: $d0 = COPY %dup
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; CHECK: RET_ReallyLR implicit $d0
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%copy:fpr(s16) = COPY $h0
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%dup:fpr(<4 x s16>) = G_DUP %copy(s16)
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$d0 = COPY %dup(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: DUPv4i16gpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0
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; CHECK-LABEL: name: DUPv4i16gpr
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; CHECK: liveins: $w0
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; CHECK: %copy:gpr32 = COPY $w0
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; CHECK: %dup:fpr64 = DUPv4i16gpr %copy
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; CHECK: $d0 = COPY %dup
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; CHECK: RET_ReallyLR implicit $d0
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%copy:gpr(s32) = COPY $w0
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%dup:fpr(<4 x s16>) = G_DUP %copy(s32)
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$d0 = COPY %dup(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: DUPv8i16lane
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $h0
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; CHECK-LABEL: name: DUPv8i16lane
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; CHECK: liveins: $h0
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; CHECK: %copy:fpr16 = COPY $h0
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.hsub
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; CHECK: %dup:fpr128 = DUPv8i16lane [[INSERT_SUBREG]], 0
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; CHECK: $q0 = COPY %dup
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; CHECK: RET_ReallyLR implicit $q0
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%copy:fpr(s16) = COPY $h0
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%dup:fpr(<8 x s16>) = G_DUP %copy(s16)
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$q0 = COPY %dup(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: DUPv8i16gpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0
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; CHECK-LABEL: name: DUPv8i16gpr
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; CHECK: liveins: $w0
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; CHECK: %copy:gpr32 = COPY $w0
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; CHECK: %dup:fpr128 = DUPv8i16gpr %copy
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; CHECK: $q0 = COPY %dup
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; CHECK: RET_ReallyLR implicit $q0
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%copy:gpr(s32) = COPY $w0
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%dup:fpr(<8 x s16>) = G_DUP %copy(s32)
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$q0 = COPY %dup(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: DUPv8i16gpr_s16_src
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0
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; Checks that we can still select the gpr variant if the scalar is an s16.
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; CHECK-LABEL: name: DUPv8i16gpr_s16_src
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; CHECK: liveins: $w0
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; CHECK: %copy:gpr32 = COPY $w0
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; CHECK: %dup:fpr128 = DUPv8i16gpr %copy
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; CHECK: $q0 = COPY %dup
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; CHECK: RET_ReallyLR implicit $q0
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%copy:gpr(s32) = COPY $w0
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%trunc:gpr(s16) = G_TRUNC %copy
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%dup:fpr(<8 x s16>) = G_DUP %trunc(s16)
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$q0 = COPY %dup(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: DUPv8i8gpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0
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; CHECK-LABEL: name: DUPv8i8gpr
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; CHECK: liveins: $w0
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; CHECK: %copy:gpr32 = COPY $w0
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; CHECK: %dup:fpr64 = DUPv8i8gpr %copy
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; CHECK: $d0 = COPY %dup
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; CHECK: RET_ReallyLR implicit $d0
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%copy:gpr(s32) = COPY $w0
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%dup:fpr(<8 x s8>) = G_DUP %copy(s32)
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$d0 = COPY %dup(<8 x s8>)
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RET_ReallyLR implicit $d0
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...
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---
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name: DUPv16i8gpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0
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; CHECK-LABEL: name: DUPv16i8gpr
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; CHECK: liveins: $w0
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; CHECK: %copy:gpr32 = COPY $w0
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; CHECK: %dup:fpr128 = DUPv16i8gpr %copy
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; CHECK: $q0 = COPY %dup
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; CHECK: RET_ReallyLR implicit $q0
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%copy:gpr(s32) = COPY $w0
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%dup:fpr(<16 x s8>) = G_DUP %copy(s32)
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$q0 = COPY %dup(<16 x s8>)
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RET_ReallyLR implicit $q0
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...
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---
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name: DUPv16i8gpr_s8_src
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0
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; Check we still select the gpr variant when scalar is an s8.
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; CHECK-LABEL: name: DUPv16i8gpr_s8_src
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; CHECK: liveins: $w0
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; CHECK: %copy:gpr32 = COPY $w0
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; CHECK: %dup:fpr128 = DUPv16i8gpr %copy
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; CHECK: $q0 = COPY %dup
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; CHECK: RET_ReallyLR implicit $q0
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%copy:gpr(s32) = COPY $w0
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%trunc:gpr(s8) = G_TRUNC %copy
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%dup:fpr(<16 x s8>) = G_DUP %trunc(s8)
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$q0 = COPY %dup(<16 x s8>)
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RET_ReallyLR implicit $q0
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...
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---
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name: dup_v2p0
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: dup_v2p0
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
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; CHECK: [[DUPv2i64gpr:%[0-9]+]]:fpr128 = DUPv2i64gpr [[COPY1]]
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; CHECK: $q0 = COPY [[DUPv2i64gpr]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:gpr(p0) = COPY $x0
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%4:fpr(<2 x p0>) = G_DUP %0(p0)
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$q0 = COPY %4(<2 x p0>)
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RET_ReallyLR implicit $q0
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...
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