150 lines
4.6 KiB
Plaintext
150 lines
4.6 KiB
Plaintext
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||
|
|
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
|
||
|
|
---
|
||
|
|
name: test_constant_vec_pool_v2f64
|
||
|
|
alignment: 4
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
liveins:
|
||
|
|
- { reg: '$x0' }
|
||
|
|
frameInfo:
|
||
|
|
maxAlignment: 1
|
||
|
|
machineFunctionInfo: {}
|
||
|
|
body: |
|
||
|
|
bb.1:
|
||
|
|
liveins: $x0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: test_constant_vec_pool_v2f64
|
||
|
|
; CHECK: liveins: $x0
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
||
|
|
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
|
||
|
|
; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
|
||
|
|
; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store 16)
|
||
|
|
; CHECK: RET_ReallyLR
|
||
|
|
%0:gpr(p0) = COPY $x0
|
||
|
|
%3:fpr(s64) = G_FCONSTANT double 5.000000e-01
|
||
|
|
%2:fpr(s64) = G_FCONSTANT double 1.600000e+01
|
||
|
|
%1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %3(s64)
|
||
|
|
G_STORE %1(<2 x s64>), %0(p0) :: (store 16)
|
||
|
|
RET_ReallyLR
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: test_constant_vec_pool_v4f32
|
||
|
|
alignment: 4
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
liveins:
|
||
|
|
- { reg: '$x0' }
|
||
|
|
frameInfo:
|
||
|
|
maxAlignment: 1
|
||
|
|
body: |
|
||
|
|
bb.1:
|
||
|
|
liveins: $x0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: test_constant_vec_pool_v4f32
|
||
|
|
; CHECK: liveins: $x0
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
||
|
|
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
|
||
|
|
; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
|
||
|
|
; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store 16)
|
||
|
|
; CHECK: RET_ReallyLR
|
||
|
|
%0:gpr(p0) = COPY $x0
|
||
|
|
%3:fpr(s32) = G_FCONSTANT float 5.000000e-01
|
||
|
|
%2:fpr(s32) = G_FCONSTANT float 1.600000e+01
|
||
|
|
%1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32), %3(s32), %3(s32)
|
||
|
|
G_STORE %1(<4 x s32>), %0(p0) :: (store 16)
|
||
|
|
RET_ReallyLR
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: test_constant_vec_pool_v2i64
|
||
|
|
alignment: 4
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
liveins:
|
||
|
|
- { reg: '$x0' }
|
||
|
|
frameInfo:
|
||
|
|
maxAlignment: 1
|
||
|
|
body: |
|
||
|
|
bb.1:
|
||
|
|
liveins: $x0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: test_constant_vec_pool_v2i64
|
||
|
|
; CHECK: liveins: $x0
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
||
|
|
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
|
||
|
|
; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
|
||
|
|
; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store 16)
|
||
|
|
; CHECK: RET_ReallyLR
|
||
|
|
%0:gpr(p0) = COPY $x0
|
||
|
|
%3:gpr(s64) = G_CONSTANT i64 67839
|
||
|
|
%2:gpr(s64) = G_CONSTANT i64 12375
|
||
|
|
%1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %3(s64)
|
||
|
|
G_STORE %1(<2 x s64>), %0(p0) :: (store 16)
|
||
|
|
RET_ReallyLR
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: test_constant_vec_pool_v4i32
|
||
|
|
alignment: 4
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
liveins:
|
||
|
|
- { reg: '$x0' }
|
||
|
|
frameInfo:
|
||
|
|
maxAlignment: 1
|
||
|
|
body: |
|
||
|
|
bb.1:
|
||
|
|
liveins: $x0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: test_constant_vec_pool_v4i32
|
||
|
|
; CHECK: liveins: $x0
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
||
|
|
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
|
||
|
|
; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
|
||
|
|
; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store 16)
|
||
|
|
; CHECK: RET_ReallyLR
|
||
|
|
%0:gpr(p0) = COPY $x0
|
||
|
|
%3:gpr(s32) = G_CONSTANT i32 67839
|
||
|
|
%2:gpr(s32) = G_CONSTANT i32 12375
|
||
|
|
%1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32), %2(s32), %3(s32)
|
||
|
|
G_STORE %1(<4 x s32>), %0(p0) :: (store 16)
|
||
|
|
RET_ReallyLR
|
||
|
|
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: test_constant_vec_pool_v2i32
|
||
|
|
alignment: 4
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
liveins:
|
||
|
|
- { reg: '$x0' }
|
||
|
|
frameInfo:
|
||
|
|
maxAlignment: 1
|
||
|
|
body: |
|
||
|
|
bb.1:
|
||
|
|
liveins: $x0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: test_constant_vec_pool_v2i32
|
||
|
|
; CHECK: liveins: $x0
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
||
|
|
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
|
||
|
|
; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
|
||
|
|
; CHECK: STRDui [[LDRDui]], [[COPY]], 0 :: (store 8)
|
||
|
|
; CHECK: RET_ReallyLR
|
||
|
|
%0:gpr(p0) = COPY $x0
|
||
|
|
%3:gpr(s32) = G_CONSTANT i32 67839
|
||
|
|
%2:gpr(s32) = G_CONSTANT i32 12375
|
||
|
|
%1:fpr(<2 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32)
|
||
|
|
G_STORE %1(<2 x s32>), %0(p0) :: (store 8)
|
||
|
|
RET_ReallyLR
|
||
|
|
|
||
|
|
...
|