164 lines
5.1 KiB
Plaintext
164 lines
5.1 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect %s -o - | FileCheck %s
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# The following should hold here:
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#
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# 1) The first and second operands of G_INSERT_VECTOR_ELT should be FPRs since
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# they are vectors.
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#
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# 2) The third operand should be on the register bank given in the test name
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# (e.g, v4s32_fpr). AArch64 supports native inserts of GPRs, so we need to
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# preserve that.
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#
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# 3) The fourth operand should be a GPR, since it's a constant.
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name: v4s32_fpr
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q1, $s0
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; CHECK-LABEL: name: v4s32_fpr
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; CHECK: liveins: $q1, $s0
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; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
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; CHECK: [[COPY1:%[0-9]+]]:fpr(<4 x s32>) = COPY $q1
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; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
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; CHECK: [[IVEC:%[0-9]+]]:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32)
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; CHECK: $q0 = COPY [[IVEC]](<4 x s32>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(s32) = COPY $s0
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%1:_(<4 x s32>) = COPY $q1
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%3:_(s32) = G_CONSTANT i32 1
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%2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: v4s32_gpr
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $w0
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; CHECK-LABEL: name: v4s32_gpr
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; CHECK: liveins: $q0, $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
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; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
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; CHECK: [[IVEC:%[0-9]+]]:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32)
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; CHECK: $q0 = COPY [[IVEC]](<4 x s32>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(s32) = COPY $w0
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%1:_(<4 x s32>) = COPY $q0
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%3:_(s32) = G_CONSTANT i32 1
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%2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: v2s64_fpr
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $q1
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; CHECK-LABEL: name: v2s64_fpr
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; CHECK: liveins: $d0, $q1
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; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s64>) = COPY $q1
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; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
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; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s64), [[C]](s32)
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; CHECK: $q0 = COPY [[IVEC]](<2 x s64>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(s64) = COPY $d0
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%1:_(<2 x s64>) = COPY $q1
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%3:_(s32) = G_CONSTANT i32 1
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%2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32)
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$q0 = COPY %2(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: v2s64_gpr
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $x0
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; CHECK-LABEL: name: v2s64_gpr
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; CHECK: liveins: $q0, $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0
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; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
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; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s64), [[C]](s32)
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; CHECK: $q0 = COPY [[IVEC]](<2 x s64>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(s64) = COPY $x0
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%1:_(<2 x s64>) = COPY $q0
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%3:_(s32) = G_CONSTANT i32 0
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%2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32)
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$q0 = COPY %2(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: v2s32_fpr
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d1, $s0
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; CHECK-LABEL: name: v2s32_fpr
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; CHECK: liveins: $d1, $s0
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; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
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; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s32>) = COPY $d1
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; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
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; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32)
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; CHECK: $d0 = COPY [[IVEC]](<2 x s32>)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(s32) = COPY $s0
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%1:_(<2 x s32>) = COPY $d1
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%3:_(s32) = G_CONSTANT i32 1
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%2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
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$d0 = COPY %2(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: v2s32_gpr
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $w0
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; CHECK-LABEL: name: v2s32_gpr
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; CHECK: liveins: $d0, $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s32>) = COPY $d0
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; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
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; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32)
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; CHECK: $d0 = COPY [[IVEC]](<2 x s32>)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(s32) = COPY $w0
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%1:_(<2 x s32>) = COPY $d0
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%3:_(s32) = G_CONSTANT i32 1
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%2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
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$d0 = COPY %2(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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