104 lines
3.0 KiB
Plaintext
104 lines
3.0 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: sextload_from_inreg
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: sextload_from_inreg
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s16) = G_SEXTLOAD [[COPY]](p0) :: (load 1, align 2)
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXTLOAD]](s16)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(p0) = COPY $x0
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%1:_(s16) = G_LOAD %0(p0) :: (load 2)
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%2:_(s16) = G_SEXT_INREG %1, 8
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%3:_(s32) = G_ANYEXT %2(s16)
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$w0 = COPY %3(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: non_pow_2_inreg
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: non_pow_2_inreg
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4)
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; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LOAD]], 24
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; CHECK: $w0 = COPY [[SEXT_INREG]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(p0) = COPY $x0
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%1:_(s32) = G_LOAD %0(p0) :: (load 4)
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%2:_(s32) = G_SEXT_INREG %1, 24
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: atomic
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: atomic
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load acquire 2)
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; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s16) = G_SEXT_INREG [[LOAD]], 8
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXT_INREG]](s16)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(p0) = COPY $x0
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%1:_(s16) = G_LOAD %0(p0) :: (load acquire 2)
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%2:_(s16) = G_SEXT_INREG %1, 8
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%3:_(s32) = G_ANYEXT %2(s16)
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$w0 = COPY %3(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: volatile
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: volatile
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (volatile load 2)
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; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s16) = G_SEXT_INREG [[LOAD]], 8
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXT_INREG]](s16)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(p0) = COPY $x0
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%1:_(s16) = G_LOAD %0(p0) :: (volatile load 2)
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%2:_(s16) = G_SEXT_INREG %1, 8
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%3:_(s32) = G_ANYEXT %2(s16)
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$w0 = COPY %3(s32)
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RET_ReallyLR implicit $w0
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...
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