38 lines
1.1 KiB
Plaintext
38 lines
1.1 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=aarch64 -run-pass=aarch64-prelegalizer-combiner %s -o - -verify-machineinstrs | FileCheck %s
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64"
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define i32 @ld_zext_i24(i24* %ptr, i24* %ptr2) {
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%load = load i24, i24* %ptr, align 1
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%ext = zext i24 %load to i32
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ret i32 %ext
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}
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...
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---
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name: ld_zext_i24
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.1 (%ir-block.0):
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liveins: $x0, $x1
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; CHECK-LABEL: name: ld_zext_i24
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; CHECK: liveins: $x0, $x1
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[LOAD:%[0-9]+]]:_(s24) = G_LOAD [[COPY]](p0) :: (load 3 from %ir.ptr, align 1)
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; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s24)
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; CHECK: $w0 = COPY [[ZEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(p0) = COPY $x0
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%1:_(p0) = COPY $x1
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%2:_(s24) = G_LOAD %0(p0) :: (load 3 from %ir.ptr, align 1)
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%3:_(s32) = G_ZEXT %2(s24)
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$w0 = COPY %3(s32)
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RET_ReallyLR implicit $w0
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...
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