llvm-for-llvmta/test/CodeGen/AArch64/GlobalISel/legalize-reduce-fadd.mir

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2022-04-25 10:02:23 +02:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -march=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s
---
name: fadd_v2s32
tracksRegLiveness: true
body: |
bb.1:
liveins: $d0
; CHECK-LABEL: name: fadd_v2s32
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[VECREDUCE_FADD:%[0-9]+]]:_(s32) = G_VECREDUCE_FADD [[COPY]](<2 x s32>)
; CHECK: $w0 = COPY [[VECREDUCE_FADD]](s32)
; CHECK: RET_ReallyLR implicit $w0
%0:_(<2 x s32>) = COPY $d0
%1:_(s32) = G_VECREDUCE_FADD %0(<2 x s32>)
$w0 = COPY %1(s32)
RET_ReallyLR implicit $w0
...
---
name: fadd_v2s64
tracksRegLiveness: true
body: |
bb.1:
liveins: $q0
; CHECK-LABEL: name: fadd_v2s64
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK: [[VECREDUCE_FADD:%[0-9]+]]:_(s64) = G_VECREDUCE_FADD [[COPY]](<2 x s64>)
; CHECK: $x0 = COPY [[VECREDUCE_FADD]](s64)
; CHECK: RET_ReallyLR implicit $x0
%0:_(<2 x s64>) = COPY $q0
%2:_(s64) = G_VECREDUCE_FADD %0(<2 x s64>)
$x0 = COPY %2(s64)
RET_ReallyLR implicit $x0
...