87 lines
3.7 KiB
Plaintext
87 lines
3.7 KiB
Plaintext
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# RUN: llc -mtriple=arm64-unknown-unknown -global-isel -O0 -mattr=-fullfp16 -run-pass=legalizer %s -o - | FileCheck %s
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--- |
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define <8 x half> @test_v8f16.ceil(<8 x half> %a) {
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ret <8 x half> %a
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}
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define <4 x half> @test_v4f16.ceil(<4 x half> %a) {
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ret <4 x half> %a
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}
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...
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---
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name: test_v8f16.ceil
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $q0
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; CHECK-LABEL: name: test_v8f16.ceil
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%0:_(<8 x s16>) = COPY $q0
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; CHECK: %{{[0-9]+}}:_(s16), %{{[0-9]+}}:_(s16), %{{[0-9]+}}:_(s16), %{{[0-9]+}}:_(s16), %{{[0-9]+}}:_(s16), %{{[0-9]+}}:_(s16), %{{[0-9]+}}:_(s16), %{{[0-9]+}}:_(s16) = G_UNMERGE_VALUES %{{[0-9]+}}(<8 x s16>)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FCEIL %{{[0-9]+}}
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; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FCEIL %{{[0-9]+}}
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; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FCEIL %{{[0-9]+}}
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; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FCEIL %{{[0-9]+}}
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; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FCEIL %{{[0-9]+}}
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; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FCEIL %{{[0-9]+}}
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; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FCEIL %{{[0-9]+}}
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; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FCEIL %{{[0-9]+}}
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; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
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; CHECK: %{{[0-9]+}}:_(<8 x s16>) = G_BUILD_VECTOR %{{[0-9]+}}(s16), %{{[0-9]+}}(s16), %{{[0-9]+}}(s16), %{{[0-9]+}}(s16), %{{[0-9]+}}(s16), %{{[0-9]+}}(s16), %{{[0-9]+}}(s16), %{{[0-9]+}}(s16)
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%1:_(<8 x s16>) = G_FCEIL %0
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v4f16.ceil
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $d0
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; CHECK-LABEL: name: test_v4f16.ceil
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%0:_(<4 x s16>) = COPY $d0
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; CHECK: %{{[0-9]+}}:_(s16), %{{[0-9]+}}:_(s16), %{{[0-9]+}}:_(s16) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s16>)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FCEIL %{{[0-9]+}}
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; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FCEIL %{{[0-9]+}}
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; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FCEIL %{{[0-9]+}}
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; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FPEXT %{{[0-9]+}}(s16)
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; CHECK: %{{[0-9]+}}:_(s32) = G_FCEIL %{{[0-9]+}}
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; CHECK: %{{[0-9]+}}:_(s16) = G_FPTRUNC %{{[0-9]+}}(s32)
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; CHECK: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR %{{[0-9]+}}(s16), %{{[0-9]+}}(s16), %{{[0-9]+}}(s16), %{{[0-9]+}}(s16)
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%1:_(<4 x s16>) = G_FCEIL %0
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$d0 = COPY %1(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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