128 lines
3.6 KiB
Plaintext
128 lines
3.6 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-unknown -o - -verify-machineinstrs -run-pass=instruction-select %s | FileCheck %s
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# PR36345
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-arm-none-eabi"
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; Function Attrs: noinline nounwind optnone
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define void @fp16_to_gpr([2 x half], [2 x half]* %addr) {
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ret void
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}
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define void @gpr_to_fp16() {
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ret void
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}
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define void @gpr_to_fp16_physreg() {
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ret void
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}
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...
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---
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name: fp16_to_gpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: fpr }
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- { id: 2, class: fpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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- { id: 5, class: gpr }
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- { id: 6, class: gpr }
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- { id: 7, class: gpr }
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- { id: 8, class: gpr }
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- { id: 9, class: gpr }
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- { id: 10, class: gpr }
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- { id: 11, class: gpr }
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- { id: 12, class: gpr }
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body: |
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bb.1 (%ir-block.1):
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liveins: $h0, $h1, $x0
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; CHECK-LABEL: name: fp16_to_gpr
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; CHECK: liveins: $h0, $h1, $x0
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; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
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; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1
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; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub
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; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]]
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; CHECK: [[BFMWri:%[0-9]+]]:gpr32 = BFMWri [[DEF]], [[COPY2]], 0, 15
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; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub
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; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG1]]
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; CHECK: [[BFMWri1:%[0-9]+]]:gpr32 = BFMWri [[BFMWri]], [[COPY3]], 16, 15
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; CHECK: [[COPY4:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: STRWui [[BFMWri1]], [[COPY4]], 0 :: (store 4 into %ir.addr, align 2)
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; CHECK: RET_ReallyLR
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%1:fpr(s16) = COPY $h0
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%2:fpr(s16) = COPY $h1
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%3:gpr(s32) = G_IMPLICIT_DEF
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%11:gpr(s16) = COPY %1(s16)
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%4:gpr(s32) = G_INSERT %3, %11(s16), 0
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%12:gpr(s16) = COPY %2(s16)
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%5:gpr(s32) = G_INSERT %4, %12(s16), 16
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%0:gpr(s32) = COPY %5(s32)
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%6:gpr(p0) = COPY $x0
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G_STORE %0(s32), %6(p0) :: (store 4 into %ir.addr, align 2)
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RET_ReallyLR
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...
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---
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name: gpr_to_fp16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: fpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $w0
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; CHECK-LABEL: name: gpr_to_fp16
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; CHECK: liveins: $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
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; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
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; CHECK: $h0 = COPY [[COPY2]]
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; CHECK: RET_ReallyLR implicit $h0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s16) = G_TRUNC %0(s32)
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%2:fpr(s16) = COPY %1(s16)
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$h0 = COPY %2(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: gpr_to_fp16_physreg
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $w0
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; CHECK-LABEL: name: gpr_to_fp16_physreg
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; CHECK: liveins: $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
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; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
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; CHECK: $h0 = COPY [[COPY2]]
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; CHECK: RET_ReallyLR implicit $h0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s16) = G_TRUNC %0(s32)
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$h0 = COPY %1(s16)
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RET_ReallyLR implicit $h0
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...
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