llvm-for-llvmta/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir

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2022-04-25 10:02:23 +02:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -march=aarch64 -run-pass=aarch64-prelegalizer-combiner %s | FileCheck %s
---
name: test_combine_consecutive
body: |
bb.1:
liveins: $w0, $w1
; CHECK-LABEL: name: test_combine_consecutive
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(<2 x s32>) = G_IMPLICIT_DEF
%7:_(s32) = G_CONSTANT i32 0
%8:_(s32) = G_CONSTANT i32 1
%3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s32)
%4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %3, %1(s32), %8(s32)
$x0 = COPY %4
...
---
name: test_combine_diff_order
body: |
bb.1:
liveins: $w0, $w1
; CHECK-LABEL: name: test_combine_diff_order
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY]](s32)
; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(<2 x s32>) = G_IMPLICIT_DEF
%7:_(s32) = G_CONSTANT i32 1
%8:_(s32) = G_CONSTANT i32 0
%3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s32)
%4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %3, %1(s32), %8(s32)
$x0 = COPY %4
...
---
name: test_combine_insert_vec_build_vec_idx_1
body: |
bb.1:
liveins: $w0, $w1, $w2, $w3
; CHECK-LABEL: name: test_combine_insert_vec_build_vec_idx_1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w3
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>)
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%6:_(s32) = COPY $w2
%7:_(s32) = COPY $w3
%2:_(<4 x s32>) = G_BUILD_VECTOR %0, %1, %6, %7
%3:_(s32) = G_CONSTANT i32 1
%4:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32)
$q0 = COPY %4
...
---
name: test_combine_insert_vec_build_vec_idx_oob
body: |
bb.1:
liveins: $w0, $w1, $w2, $w3
; CHECK-LABEL: name: test_combine_insert_vec_build_vec_idx_oob
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[COPY]](s32), [[C]](s32)
; CHECK: $q0 = COPY [[IVEC]](<4 x s32>)
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%6:_(s32) = COPY $w2
%7:_(s32) = COPY $w3
%2:_(<4 x s32>) = G_BUILD_VECTOR %0, %1, %6, %7
%3:_(s32) = G_CONSTANT i32 4
%4:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32)
$q0 = COPY %4
...
---
name: test_combine_insert_vec_build_vec_variable
body: |
bb.1:
liveins: $w0, $w1, $w2, $w3
; CHECK-LABEL: name: test_combine_insert_vec_build_vec_variable
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[COPY]](s32), [[COPY]](s32)
; CHECK: $q0 = COPY [[IVEC]](<4 x s32>)
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%6:_(s32) = COPY $w2
%7:_(s32) = COPY $w3
%2:_(<4 x s32>) = G_BUILD_VECTOR %0, %1, %6, %7
%3:_(s32) = COPY %0
%4:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32)
$q0 = COPY %4
...
---
name: test_combine_multiple_same_idx_1
body: |
bb.1:
liveins: $w0, $w1
; CHECK-LABEL: name: test_combine_multiple_same_idx_1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(<2 x s32>) = G_IMPLICIT_DEF
%7:_(s32) = G_CONSTANT i32 0
%8:_(s32) = G_CONSTANT i32 1
%3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s32)
%4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %3, %1(s32), %8(s32)
%5:_(<2 x s32>) = G_INSERT_VECTOR_ELT %4, %1(s32), %8(s32)
$x0 = COPY %5
...
---
name: test_combine_multiple_same_idx_2
body: |
bb.1:
liveins: $w0, $w1
; CHECK-LABEL: name: test_combine_multiple_same_idx_2
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32)
; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(<2 x s32>) = G_IMPLICIT_DEF
%7:_(s32) = G_CONSTANT i32 0
%8:_(s32) = G_CONSTANT i32 1
%3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s32)
%4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %3, %1(s32), %7(s32)
%5:_(<2 x s32>) = G_INSERT_VECTOR_ELT %4, %1(s32), %8(s32)
$x0 = COPY %5
...
---
name: test_combine_missing_idx
body: |
bb.1:
liveins: $w0, $w1
; CHECK-LABEL: name: test_combine_missing_idx
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[DEF]](s32), [[COPY1]](s32), [[COPY]](s32)
; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>)
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(<4 x s32>) = G_IMPLICIT_DEF
%7:_(s32) = G_CONSTANT i32 0
%8:_(s32) = G_CONSTANT i32 2
%9:_(s32) = G_CONSTANT i32 3
%10:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s32)
%11:_(<4 x s32>) = G_INSERT_VECTOR_ELT %10, %1(s32), %8(s32)
%12:_(<4 x s32>) = G_INSERT_VECTOR_ELT %11, %0(s32), %9(s32)
$q0 = COPY %12
...