223 lines
6.5 KiB
LLVM
223 lines
6.5 KiB
LLVM
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; RUN: opt -mtriple amdgcn-unknown-amdhsa -analyze -divergence -use-gpu-divergence-analysis %s | FileCheck %s
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; divergent loop (H<header><exiting to X>, B<exiting to Y>)
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; the divergent join point in %exit is obscured by uniform control joining in %X
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define amdgpu_kernel void @hidden_loop_diverge(i32 %n, i32 %a, i32 %b) #0 {
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; CHECK-LABEL: Printing analysis 'Legacy Divergence Analysis' for function 'hidden_loop_diverge':
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; CHECK-NOT: DIVERGENT: %uni.
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; CHECK-NOT: DIVERGENT: br i1 %uni.
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%uni.cond = icmp slt i32 %a, 0
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br i1 %uni.cond, label %X, label %H ; uniform
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H:
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%uni.merge.h = phi i32 [ 0, %entry ], [ %uni.inc, %B ]
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%div.exitx = icmp slt i32 %tid, 0
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br i1 %div.exitx, label %X, label %B ; divergent branch
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; CHECK: DIVERGENT: %div.exitx =
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; CHECK: DIVERGENT: br i1 %div.exitx,
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B:
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%uni.inc = add i32 %uni.merge.h, 1
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%div.exity = icmp sgt i32 %tid, 0
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br i1 %div.exity, label %Y, label %H ; divergent branch
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; CHECK: DIVERGENT: %div.exity =
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; CHECK: DIVERGENT: br i1 %div.exity,
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X:
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%div.merge.x = phi i32 [ %a, %entry ], [ %uni.merge.h, %H ] ; temporal divergent phi
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br i1 %uni.cond, label %Y, label %exit
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; CHECK: DIVERGENT: %div.merge.x =
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Y:
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%div.merge.y = phi i32 [ 42, %X ], [ %b, %B ]
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br label %exit
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; CHECK: DIVERGENT: %div.merge.y =
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exit:
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%div.merge.exit = phi i32 [ %a, %X ], [ %b, %Y ]
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ret void
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; CHECK: DIVERGENT: %div.merge.exit =
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}
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; divergent loop (H<header><exiting to X>, B<exiting to Y>)
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; the phi nodes in X and Y don't actually receive divergent values
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define amdgpu_kernel void @unobserved_loop_diverge(i32 %n, i32 %a, i32 %b) #0 {
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; CHECK-LABEL: Printing analysis 'Legacy Divergence Analysis' for function 'unobserved_loop_diverge':
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; CHECK-NOT: DIVERGENT: %uni.
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; CHECK-NOT: DIVERGENT: br i1 %uni.
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%uni.cond = icmp slt i32 %a, 0
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br i1 %uni.cond, label %X, label %H ; uniform
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H:
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%uni.merge.h = phi i32 [ 0, %entry ], [ %uni.inc, %B ]
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%div.exitx = icmp slt i32 %tid, 0
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br i1 %div.exitx, label %X, label %B ; divergent branch
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; CHECK: DIVERGENT: %div.exitx =
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; CHECK: DIVERGENT: br i1 %div.exitx,
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B:
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%uni.inc = add i32 %uni.merge.h, 1
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%div.exity = icmp sgt i32 %tid, 0
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br i1 %div.exity, label %Y, label %H ; divergent branch
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; CHECK: DIVERGENT: %div.exity =
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; CHECK: DIVERGENT: br i1 %div.exity,
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X:
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%uni.merge.x = phi i32 [ %a, %entry ], [ %b, %H ]
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br label %exit
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Y:
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%uni.merge.y = phi i32 [ %b, %B ]
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br label %exit
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exit:
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%div.merge.exit = phi i32 [ %a, %X ], [ %b, %Y ]
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ret void
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; CHECK: DIVERGENT: %div.merge.exit =
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}
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; divergent loop (G<header>, L<exiting to D>) inside divergent loop (H<header>, B<exiting to X>, C<exiting to Y>, D, G, L)
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; the inner loop has no exit to top level.
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; the outer loop becomes divergent as its exiting branch in C is control-dependent on the inner loop's divergent loop exit in D.
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define amdgpu_kernel void @hidden_nestedloop_diverge(i32 %n, i32 %a, i32 %b) #0 {
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; CHECK-LABEL: Printing analysis 'Legacy Divergence Analysis' for function 'hidden_nestedloop_diverge':
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; CHECK-NOT: DIVERGENT: %uni.
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; CHECK-NOT: DIVERGENT: br i1 %uni.
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%uni.cond = icmp slt i32 %a, 0
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%div.exitx = icmp slt i32 %tid, 0
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br i1 %uni.cond, label %X, label %H
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H:
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%uni.merge.h = phi i32 [ 0, %entry ], [ %uni.inc, %D ]
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br i1 %uni.cond, label %G, label %B
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; CHECK: DIVERGENT: %div.exitx =
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B:
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br i1 %uni.cond, label %X, label %C
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C:
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br i1 %uni.cond, label %Y, label %D
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D:
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%uni.inc = add i32 %uni.merge.h, 1
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br label %H
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G:
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br i1 %div.exitx, label %C, label %L
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; CHECK: DIVERGENT: br i1 %div.exitx,
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L:
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br i1 %uni.cond, label %D, label %G
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X:
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%uni.merge.x = phi i32 [ %a, %entry ], [ %uni.merge.h, %B ]
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br i1 %uni.cond, label %Y, label %exit
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Y:
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%div.merge.y = phi i32 [ 42, %X ], [ %b, %C ]
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br label %exit
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; CHECK: DIVERGENT: %div.merge.y =
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exit:
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%div.merge.exit = phi i32 [ %a, %X ], [ %b, %Y ]
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ret void
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; CHECK: DIVERGENT: %div.merge.exit =
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}
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; divergent loop (G<header>, L<exiting to X>) in divergent loop (H<header>, B<exiting to C>, C, G, L)
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; the outer loop has no immediately divergent exiting edge.
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; the inner exiting edge is exiting to top-level through the outer loop causing both to become divergent.
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define amdgpu_kernel void @hidden_doublebreak_diverge(i32 %n, i32 %a, i32 %b) #0 {
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; CHECK-LABEL: Printing analysis 'Legacy Divergence Analysis' for function 'hidden_doublebreak_diverge':
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; CHECK-NOT: DIVERGENT: %uni.
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; CHECK-NOT: DIVERGENT: br i1 %uni.
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%uni.cond = icmp slt i32 %a, 0
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%div.exitx = icmp slt i32 %tid, 0
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br i1 %uni.cond, label %X, label %H
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H:
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%uni.merge.h = phi i32 [ 0, %entry ], [ %uni.inc, %C ]
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br i1 %uni.cond, label %G, label %B
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; CHECK: DIVERGENT: %div.exitx =
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B:
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br i1 %uni.cond, label %Y, label %C
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C:
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%uni.inc = add i32 %uni.merge.h, 1
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br label %H
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G:
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br i1 %div.exitx, label %X, label %L ; two-level break
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; CHECK: DIVERGENT: br i1 %div.exitx,
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L:
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br i1 %uni.cond, label %C, label %G
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X:
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%div.merge.x = phi i32 [ %a, %entry ], [ %uni.merge.h, %G ] ; temporal divergence
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br label %Y
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; CHECK: DIVERGENT: %div.merge.x =
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Y:
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%div.merge.y = phi i32 [ 42, %X ], [ %b, %B ]
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ret void
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; CHECK: DIVERGENT: %div.merge.y =
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}
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; divergent loop (G<header>, L<exiting to D>) contained inside a uniform loop (H<header>, B, G, L , D<exiting to x>)
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define amdgpu_kernel void @hidden_containedloop_diverge(i32 %n, i32 %a, i32 %b) #0 {
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; CHECK-LABEL: Printing analysis 'Legacy Divergence Analysis' for function 'hidden_containedloop_diverge':
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; CHECK-NOT: DIVERGENT: %uni.
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; CHECK-NOT: DIVERGENT: br i1 %uni.
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%uni.cond = icmp slt i32 %a, 0
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%div.exitx = icmp slt i32 %tid, 0
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br i1 %uni.cond, label %X, label %H
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H:
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%uni.merge.h = phi i32 [ 0, %entry ], [ %uni.inc.d, %D ]
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br i1 %uni.cond, label %G, label %B
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; CHECK: DIVERGENT: %div.exitx =
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B:
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%div.merge.b = phi i32 [ 42, %H ], [ %uni.merge.g, %G ]
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br label %D
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; CHECK: DIVERGENT: %div.merge.b =
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G:
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%uni.merge.g = phi i32 [ 123, %H ], [ %uni.inc.l, %L ]
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br i1 %div.exitx, label %B, label %L
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; CHECK: DIVERGENT: br i1 %div.exitx,
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L:
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%uni.inc.l = add i32 %uni.merge.g, 1
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br i1 %uni.cond, label %G, label %D
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D:
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%uni.inc.d = add i32 %uni.merge.h, 1
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br i1 %uni.cond, label %X, label %H
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X:
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%uni.merge.x = phi i32 [ %a, %entry ], [ %uni.inc.d, %D ]
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone }
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