455 lines
16 KiB
C++
455 lines
16 KiB
C++
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//===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file includes code for rendering MCInst instances as Intel-style
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// assembly.
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//
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//===----------------------------------------------------------------------===//
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#include "X86IntelInstPrinter.h"
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#include "X86BaseInfo.h"
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#include "X86InstComments.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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// Include the auto-generated portion of the assembly writer.
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#define PRINT_ALIAS_INSTR
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#include "X86GenAsmWriter1.inc"
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void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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OS << getRegisterName(RegNo);
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}
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void X86IntelInstPrinter::printInst(const MCInst *MI, uint64_t Address,
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StringRef Annot, const MCSubtargetInfo &STI,
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raw_ostream &OS) {
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printInstFlags(MI, OS);
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// In 16-bit mode, print data16 as data32.
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if (MI->getOpcode() == X86::DATA16_PREFIX &&
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STI.getFeatureBits()[X86::Mode16Bit]) {
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OS << "\tdata32";
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} else if (!printAliasInstr(MI, Address, OS) && !printVecCompareInstr(MI, OS))
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printInstruction(MI, Address, OS);
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// Next always print the annotation.
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printAnnotation(OS, Annot);
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// If verbose assembly is enabled, we can print some informative comments.
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if (CommentStream)
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EmitAnyX86InstComments(MI, *CommentStream, MII);
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}
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bool X86IntelInstPrinter::printVecCompareInstr(const MCInst *MI, raw_ostream &OS) {
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if (MI->getNumOperands() == 0 ||
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!MI->getOperand(MI->getNumOperands() - 1).isImm())
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return false;
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int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm();
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const MCInstrDesc &Desc = MII.get(MI->getOpcode());
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// Custom print the vector compare instructions to get the immediate
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// translated into the mnemonic.
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switch (MI->getOpcode()) {
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case X86::CMPPDrmi: case X86::CMPPDrri:
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case X86::CMPPSrmi: case X86::CMPPSrri:
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case X86::CMPSDrm: case X86::CMPSDrr:
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case X86::CMPSDrm_Int: case X86::CMPSDrr_Int:
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case X86::CMPSSrm: case X86::CMPSSrr:
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case X86::CMPSSrm_Int: case X86::CMPSSrr_Int:
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if (Imm >= 0 && Imm <= 7) {
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OS << '\t';
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printCMPMnemonic(MI, /*IsVCMP*/false, OS);
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printOperand(MI, 0, OS);
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OS << ", ";
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// Skip operand 1 as its tied to the dest.
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if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
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if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS)
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printdwordmem(MI, 2, OS);
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else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD)
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printqwordmem(MI, 2, OS);
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else
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printxmmwordmem(MI, 2, OS);
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} else
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printOperand(MI, 2, OS);
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return true;
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}
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break;
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case X86::VCMPPDrmi: case X86::VCMPPDrri:
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case X86::VCMPPDYrmi: case X86::VCMPPDYrri:
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case X86::VCMPPDZ128rmi: case X86::VCMPPDZ128rri:
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case X86::VCMPPDZ256rmi: case X86::VCMPPDZ256rri:
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case X86::VCMPPDZrmi: case X86::VCMPPDZrri:
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case X86::VCMPPSrmi: case X86::VCMPPSrri:
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case X86::VCMPPSYrmi: case X86::VCMPPSYrri:
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case X86::VCMPPSZ128rmi: case X86::VCMPPSZ128rri:
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case X86::VCMPPSZ256rmi: case X86::VCMPPSZ256rri:
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case X86::VCMPPSZrmi: case X86::VCMPPSZrri:
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case X86::VCMPSDrm: case X86::VCMPSDrr:
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case X86::VCMPSDZrm: case X86::VCMPSDZrr:
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case X86::VCMPSDrm_Int: case X86::VCMPSDrr_Int:
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case X86::VCMPSDZrm_Int: case X86::VCMPSDZrr_Int:
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case X86::VCMPSSrm: case X86::VCMPSSrr:
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case X86::VCMPSSZrm: case X86::VCMPSSZrr:
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case X86::VCMPSSrm_Int: case X86::VCMPSSrr_Int:
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case X86::VCMPSSZrm_Int: case X86::VCMPSSZrr_Int:
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case X86::VCMPPDZ128rmik: case X86::VCMPPDZ128rrik:
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case X86::VCMPPDZ256rmik: case X86::VCMPPDZ256rrik:
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case X86::VCMPPDZrmik: case X86::VCMPPDZrrik:
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case X86::VCMPPSZ128rmik: case X86::VCMPPSZ128rrik:
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case X86::VCMPPSZ256rmik: case X86::VCMPPSZ256rrik:
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case X86::VCMPPSZrmik: case X86::VCMPPSZrrik:
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case X86::VCMPSDZrm_Intk: case X86::VCMPSDZrr_Intk:
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case X86::VCMPSSZrm_Intk: case X86::VCMPSSZrr_Intk:
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case X86::VCMPPDZ128rmbi: case X86::VCMPPDZ128rmbik:
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case X86::VCMPPDZ256rmbi: case X86::VCMPPDZ256rmbik:
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case X86::VCMPPDZrmbi: case X86::VCMPPDZrmbik:
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case X86::VCMPPSZ128rmbi: case X86::VCMPPSZ128rmbik:
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case X86::VCMPPSZ256rmbi: case X86::VCMPPSZ256rmbik:
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case X86::VCMPPSZrmbi: case X86::VCMPPSZrmbik:
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case X86::VCMPPDZrrib: case X86::VCMPPDZrribk:
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case X86::VCMPPSZrrib: case X86::VCMPPSZrribk:
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case X86::VCMPSDZrrb_Int: case X86::VCMPSDZrrb_Intk:
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case X86::VCMPSSZrrb_Int: case X86::VCMPSSZrrb_Intk:
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if (Imm >= 0 && Imm <= 31) {
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OS << '\t';
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printCMPMnemonic(MI, /*IsVCMP*/true, OS);
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unsigned CurOp = 0;
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printOperand(MI, CurOp++, OS);
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if (Desc.TSFlags & X86II::EVEX_K) {
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// Print mask operand.
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OS << " {";
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printOperand(MI, CurOp++, OS);
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OS << "}";
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}
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OS << ", ";
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printOperand(MI, CurOp++, OS);
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OS << ", ";
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if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
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if (Desc.TSFlags & X86II::EVEX_B) {
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// Broadcast form.
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// Load size is based on W-bit.
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if (Desc.TSFlags & X86II::VEX_W)
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printqwordmem(MI, CurOp++, OS);
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else
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printdwordmem(MI, CurOp++, OS);
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// Print the number of elements broadcasted.
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unsigned NumElts;
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if (Desc.TSFlags & X86II::EVEX_L2)
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NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16;
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else if (Desc.TSFlags & X86II::VEX_L)
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NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8;
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else
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NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4;
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OS << "{1to" << NumElts << "}";
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} else {
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if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS)
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printdwordmem(MI, CurOp++, OS);
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else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD)
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printqwordmem(MI, CurOp++, OS);
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else if (Desc.TSFlags & X86II::EVEX_L2)
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printzmmwordmem(MI, CurOp++, OS);
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else if (Desc.TSFlags & X86II::VEX_L)
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printymmwordmem(MI, CurOp++, OS);
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else
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printxmmwordmem(MI, CurOp++, OS);
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}
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} else {
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printOperand(MI, CurOp++, OS);
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if (Desc.TSFlags & X86II::EVEX_B)
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OS << ", {sae}";
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}
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return true;
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}
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break;
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case X86::VPCOMBmi: case X86::VPCOMBri:
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case X86::VPCOMDmi: case X86::VPCOMDri:
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case X86::VPCOMQmi: case X86::VPCOMQri:
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case X86::VPCOMUBmi: case X86::VPCOMUBri:
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case X86::VPCOMUDmi: case X86::VPCOMUDri:
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case X86::VPCOMUQmi: case X86::VPCOMUQri:
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case X86::VPCOMUWmi: case X86::VPCOMUWri:
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case X86::VPCOMWmi: case X86::VPCOMWri:
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if (Imm >= 0 && Imm <= 7) {
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OS << '\t';
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printVPCOMMnemonic(MI, OS);
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printOperand(MI, 0, OS);
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OS << ", ";
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printOperand(MI, 1, OS);
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OS << ", ";
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if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem)
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printxmmwordmem(MI, 2, OS);
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else
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printOperand(MI, 2, OS);
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return true;
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}
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break;
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case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri:
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case X86::VPCMPBZ256rmi: case X86::VPCMPBZ256rri:
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case X86::VPCMPBZrmi: case X86::VPCMPBZrri:
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case X86::VPCMPDZ128rmi: case X86::VPCMPDZ128rri:
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case X86::VPCMPDZ256rmi: case X86::VPCMPDZ256rri:
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case X86::VPCMPDZrmi: case X86::VPCMPDZrri:
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case X86::VPCMPQZ128rmi: case X86::VPCMPQZ128rri:
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case X86::VPCMPQZ256rmi: case X86::VPCMPQZ256rri:
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case X86::VPCMPQZrmi: case X86::VPCMPQZrri:
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case X86::VPCMPUBZ128rmi: case X86::VPCMPUBZ128rri:
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case X86::VPCMPUBZ256rmi: case X86::VPCMPUBZ256rri:
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case X86::VPCMPUBZrmi: case X86::VPCMPUBZrri:
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case X86::VPCMPUDZ128rmi: case X86::VPCMPUDZ128rri:
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case X86::VPCMPUDZ256rmi: case X86::VPCMPUDZ256rri:
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case X86::VPCMPUDZrmi: case X86::VPCMPUDZrri:
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case X86::VPCMPUQZ128rmi: case X86::VPCMPUQZ128rri:
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case X86::VPCMPUQZ256rmi: case X86::VPCMPUQZ256rri:
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case X86::VPCMPUQZrmi: case X86::VPCMPUQZrri:
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case X86::VPCMPUWZ128rmi: case X86::VPCMPUWZ128rri:
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case X86::VPCMPUWZ256rmi: case X86::VPCMPUWZ256rri:
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case X86::VPCMPUWZrmi: case X86::VPCMPUWZrri:
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case X86::VPCMPWZ128rmi: case X86::VPCMPWZ128rri:
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case X86::VPCMPWZ256rmi: case X86::VPCMPWZ256rri:
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case X86::VPCMPWZrmi: case X86::VPCMPWZrri:
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case X86::VPCMPBZ128rmik: case X86::VPCMPBZ128rrik:
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case X86::VPCMPBZ256rmik: case X86::VPCMPBZ256rrik:
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case X86::VPCMPBZrmik: case X86::VPCMPBZrrik:
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case X86::VPCMPDZ128rmik: case X86::VPCMPDZ128rrik:
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case X86::VPCMPDZ256rmik: case X86::VPCMPDZ256rrik:
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case X86::VPCMPDZrmik: case X86::VPCMPDZrrik:
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case X86::VPCMPQZ128rmik: case X86::VPCMPQZ128rrik:
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case X86::VPCMPQZ256rmik: case X86::VPCMPQZ256rrik:
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case X86::VPCMPQZrmik: case X86::VPCMPQZrrik:
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case X86::VPCMPUBZ128rmik: case X86::VPCMPUBZ128rrik:
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case X86::VPCMPUBZ256rmik: case X86::VPCMPUBZ256rrik:
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case X86::VPCMPUBZrmik: case X86::VPCMPUBZrrik:
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case X86::VPCMPUDZ128rmik: case X86::VPCMPUDZ128rrik:
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case X86::VPCMPUDZ256rmik: case X86::VPCMPUDZ256rrik:
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case X86::VPCMPUDZrmik: case X86::VPCMPUDZrrik:
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case X86::VPCMPUQZ128rmik: case X86::VPCMPUQZ128rrik:
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case X86::VPCMPUQZ256rmik: case X86::VPCMPUQZ256rrik:
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case X86::VPCMPUQZrmik: case X86::VPCMPUQZrrik:
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case X86::VPCMPUWZ128rmik: case X86::VPCMPUWZ128rrik:
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case X86::VPCMPUWZ256rmik: case X86::VPCMPUWZ256rrik:
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case X86::VPCMPUWZrmik: case X86::VPCMPUWZrrik:
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case X86::VPCMPWZ128rmik: case X86::VPCMPWZ128rrik:
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case X86::VPCMPWZ256rmik: case X86::VPCMPWZ256rrik:
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case X86::VPCMPWZrmik: case X86::VPCMPWZrrik:
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case X86::VPCMPDZ128rmib: case X86::VPCMPDZ128rmibk:
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case X86::VPCMPDZ256rmib: case X86::VPCMPDZ256rmibk:
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case X86::VPCMPDZrmib: case X86::VPCMPDZrmibk:
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case X86::VPCMPQZ128rmib: case X86::VPCMPQZ128rmibk:
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case X86::VPCMPQZ256rmib: case X86::VPCMPQZ256rmibk:
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case X86::VPCMPQZrmib: case X86::VPCMPQZrmibk:
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case X86::VPCMPUDZ128rmib: case X86::VPCMPUDZ128rmibk:
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case X86::VPCMPUDZ256rmib: case X86::VPCMPUDZ256rmibk:
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case X86::VPCMPUDZrmib: case X86::VPCMPUDZrmibk:
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case X86::VPCMPUQZ128rmib: case X86::VPCMPUQZ128rmibk:
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case X86::VPCMPUQZ256rmib: case X86::VPCMPUQZ256rmibk:
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case X86::VPCMPUQZrmib: case X86::VPCMPUQZrmibk:
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if ((Imm >= 0 && Imm <= 2) || (Imm >= 4 && Imm <= 6)) {
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OS << '\t';
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printVPCMPMnemonic(MI, OS);
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unsigned CurOp = 0;
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printOperand(MI, CurOp++, OS);
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if (Desc.TSFlags & X86II::EVEX_K) {
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// Print mask operand.
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|
OS << " {";
|
||
|
|
printOperand(MI, CurOp++, OS);
|
||
|
|
OS << "}";
|
||
|
|
}
|
||
|
|
OS << ", ";
|
||
|
|
printOperand(MI, CurOp++, OS);
|
||
|
|
OS << ", ";
|
||
|
|
|
||
|
|
if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
|
||
|
|
if (Desc.TSFlags & X86II::EVEX_B) {
|
||
|
|
// Broadcast form.
|
||
|
|
// Load size is based on W-bit as only D and Q are supported.
|
||
|
|
if (Desc.TSFlags & X86II::VEX_W)
|
||
|
|
printqwordmem(MI, CurOp++, OS);
|
||
|
|
else
|
||
|
|
printdwordmem(MI, CurOp++, OS);
|
||
|
|
|
||
|
|
// Print the number of elements broadcasted.
|
||
|
|
unsigned NumElts;
|
||
|
|
if (Desc.TSFlags & X86II::EVEX_L2)
|
||
|
|
NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16;
|
||
|
|
else if (Desc.TSFlags & X86II::VEX_L)
|
||
|
|
NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8;
|
||
|
|
else
|
||
|
|
NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4;
|
||
|
|
OS << "{1to" << NumElts << "}";
|
||
|
|
} else {
|
||
|
|
if (Desc.TSFlags & X86II::EVEX_L2)
|
||
|
|
printzmmwordmem(MI, CurOp++, OS);
|
||
|
|
else if (Desc.TSFlags & X86II::VEX_L)
|
||
|
|
printymmwordmem(MI, CurOp++, OS);
|
||
|
|
else
|
||
|
|
printxmmwordmem(MI, CurOp++, OS);
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
printOperand(MI, CurOp++, OS);
|
||
|
|
}
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
|
||
|
|
raw_ostream &O) {
|
||
|
|
const MCOperand &Op = MI->getOperand(OpNo);
|
||
|
|
if (Op.isReg()) {
|
||
|
|
printRegName(O, Op.getReg());
|
||
|
|
} else if (Op.isImm()) {
|
||
|
|
O << formatImm((int64_t)Op.getImm());
|
||
|
|
} else {
|
||
|
|
assert(Op.isExpr() && "unknown operand kind in printOperand");
|
||
|
|
O << "offset ";
|
||
|
|
Op.getExpr()->print(O, &MAI);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
|
||
|
|
raw_ostream &O) {
|
||
|
|
// Do not print the exact form of the memory operand if it references a known
|
||
|
|
// binary object.
|
||
|
|
if (SymbolizeOperands && MIA) {
|
||
|
|
uint64_t Target;
|
||
|
|
if (MIA->evaluateBranch(*MI, 0, 0, Target))
|
||
|
|
return;
|
||
|
|
if (MIA->evaluateMemoryOperandAddress(*MI, 0, 0))
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
|
||
|
|
unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
|
||
|
|
const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
|
||
|
|
const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
|
||
|
|
|
||
|
|
// If this has a segment register, print it.
|
||
|
|
printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O);
|
||
|
|
|
||
|
|
O << '[';
|
||
|
|
|
||
|
|
bool NeedPlus = false;
|
||
|
|
if (BaseReg.getReg()) {
|
||
|
|
printOperand(MI, Op+X86::AddrBaseReg, O);
|
||
|
|
NeedPlus = true;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (IndexReg.getReg()) {
|
||
|
|
if (NeedPlus) O << " + ";
|
||
|
|
if (ScaleVal != 1)
|
||
|
|
O << ScaleVal << '*';
|
||
|
|
printOperand(MI, Op+X86::AddrIndexReg, O);
|
||
|
|
NeedPlus = true;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!DispSpec.isImm()) {
|
||
|
|
if (NeedPlus) O << " + ";
|
||
|
|
assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
|
||
|
|
DispSpec.getExpr()->print(O, &MAI);
|
||
|
|
} else {
|
||
|
|
int64_t DispVal = DispSpec.getImm();
|
||
|
|
if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
||
|
|
if (NeedPlus) {
|
||
|
|
if (DispVal > 0)
|
||
|
|
O << " + ";
|
||
|
|
else {
|
||
|
|
O << " - ";
|
||
|
|
DispVal = -DispVal;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
O << formatImm(DispVal);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
O << ']';
|
||
|
|
}
|
||
|
|
|
||
|
|
void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
|
||
|
|
raw_ostream &O) {
|
||
|
|
// If this has a segment register, print it.
|
||
|
|
printOptionalSegReg(MI, Op + 1, O);
|
||
|
|
O << '[';
|
||
|
|
printOperand(MI, Op, O);
|
||
|
|
O << ']';
|
||
|
|
}
|
||
|
|
|
||
|
|
void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
|
||
|
|
raw_ostream &O) {
|
||
|
|
// DI accesses are always ES-based.
|
||
|
|
O << "es:[";
|
||
|
|
printOperand(MI, Op, O);
|
||
|
|
O << ']';
|
||
|
|
}
|
||
|
|
|
||
|
|
void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
|
||
|
|
raw_ostream &O) {
|
||
|
|
const MCOperand &DispSpec = MI->getOperand(Op);
|
||
|
|
|
||
|
|
// If this has a segment register, print it.
|
||
|
|
printOptionalSegReg(MI, Op + 1, O);
|
||
|
|
|
||
|
|
O << '[';
|
||
|
|
|
||
|
|
if (DispSpec.isImm()) {
|
||
|
|
O << formatImm(DispSpec.getImm());
|
||
|
|
} else {
|
||
|
|
assert(DispSpec.isExpr() && "non-immediate displacement?");
|
||
|
|
DispSpec.getExpr()->print(O, &MAI);
|
||
|
|
}
|
||
|
|
|
||
|
|
O << ']';
|
||
|
|
}
|
||
|
|
|
||
|
|
void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
|
||
|
|
raw_ostream &O) {
|
||
|
|
if (MI->getOperand(Op).isExpr())
|
||
|
|
return MI->getOperand(Op).getExpr()->print(O, &MAI);
|
||
|
|
|
||
|
|
O << formatImm(MI->getOperand(Op).getImm() & 0xff);
|
||
|
|
}
|
||
|
|
|
||
|
|
void X86IntelInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
|
||
|
|
raw_ostream &OS) {
|
||
|
|
const MCOperand &Op = MI->getOperand(OpNo);
|
||
|
|
unsigned Reg = Op.getReg();
|
||
|
|
// Override the default printing to print st(0) instead st.
|
||
|
|
if (Reg == X86::ST0)
|
||
|
|
OS << "st(0)";
|
||
|
|
else
|
||
|
|
printRegName(OS, Reg);
|
||
|
|
}
|