220 lines
9.6 KiB
C
220 lines
9.6 KiB
C
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//===-- VEISelLowering.h - VE DAG Lowering Interface ------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that VE uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_VE_VEISELLOWERING_H
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#define LLVM_LIB_TARGET_VE_VEISELLOWERING_H
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#include "VE.h"
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#include "llvm/CodeGen/TargetLowering.h"
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namespace llvm {
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class VESubtarget;
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namespace VEISD {
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enum NodeType : unsigned {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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CALL, // A call instruction.
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EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
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EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
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EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
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GETFUNPLT, // Load function address through %plt insturction.
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GETTLSADDR, // Load address for TLS access.
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GETSTACKTOP, // Retrieve address of stack top (first address of
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// locals and temporaries).
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GLOBAL_BASE_REG, // Global base reg for PIC.
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Hi, // Hi/Lo operations, typically on a global address.
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Lo, // Hi/Lo operations, typically on a global address.
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MEMBARRIER, // Compiler barrier only; generate a no-op.
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RET_FLAG, // Return with a flag operand.
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TS1AM, // A TS1AM instruction used for 1/2 bytes swap.
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VEC_BROADCAST, // A vector broadcast instruction.
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// 0: scalar value, 1: VL
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// VVP_* nodes.
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#define ADD_VVP_OP(VVP_NAME, ...) VVP_NAME,
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#include "VVPNodes.def"
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};
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}
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class VETargetLowering : public TargetLowering {
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const VESubtarget *Subtarget;
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void initRegisterClasses();
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void initSPUActions();
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void initVPUActions();
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public:
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VETargetLowering(const TargetMachine &TM, const VESubtarget &STI);
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const char *getTargetNodeName(unsigned Opcode) const override;
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MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
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return MVT::i32;
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}
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Register getRegisterByName(const char *RegName, LLT VT,
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const MachineFunction &MF) const override;
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/// getSetCCResultType - Return the ISD::SETCC ValueType
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EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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EVT VT) const override;
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
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LLVMContext &Context) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
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SelectionDAG &DAG) const override;
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/// Helper functions for atomic operations.
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bool shouldInsertFencesForAtomic(const Instruction *I) const override {
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// VE uses release consistency, so need fence for each atomics.
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return true;
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}
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Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
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AtomicOrdering Ord) const override;
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Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
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AtomicOrdering Ord) const override;
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TargetLoweringBase::AtomicExpansionKind
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shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
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/// Custom Lower {
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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unsigned getJumpTableEncoding() const override;
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const MCExpr *LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
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const MachineBasicBlock *MBB,
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unsigned Uid,
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MCContext &Ctx) const override;
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SDValue getPICJumpTableRelocBase(SDValue Table,
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SelectionDAG &DAG) const override;
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// VE doesn't need getPICJumpTableRelocBaseExpr since it is used for only
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// EK_LabelDifference32.
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SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerATOMIC_SWAP(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerToTLSGeneralDynamicModel(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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/// } Custom Lower
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/// Replace the results of node with an illegal result
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/// type with new values built out of custom code.
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///
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void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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/// Custom Inserter {
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *MBB) const override;
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MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
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MachineBasicBlock *MBB) const;
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MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
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MachineBasicBlock *MBB) const;
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MachineBasicBlock *emitSjLjDispatchBlock(MachineInstr &MI,
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MachineBasicBlock *BB) const;
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void setupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
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MachineBasicBlock *DispatchBB, int FI,
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int Offset) const;
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// Setup basic block address.
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Register prepareMBB(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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MachineBasicBlock *TargetBB, const DebugLoc &DL) const;
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// Prepare function/variable address.
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Register prepareSymbol(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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StringRef Symbol, const DebugLoc &DL, bool IsLocal,
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bool IsCall) const;
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/// } Custom Inserter
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/// VVP Lowering {
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SDValue lowerToVVP(SDValue Op, SelectionDAG &DAG) const;
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/// } VVPLowering
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/// Custom DAGCombine {
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
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/// } Custom DAGCombine
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SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
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SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
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SelectionDAG &DAG) const;
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SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
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bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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bool isFPImmLegal(const APFloat &Imm, EVT VT,
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bool ForCodeSize) const override;
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/// Returns true if the target allows unaligned memory accesses of the
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/// specified type.
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bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
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MachineMemOperand::Flags Flags,
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bool *Fast) const override;
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/// Inline Assembly {
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ConstraintType getConstraintType(StringRef Constraint) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint, MVT VT) const override;
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/// } Inline Assembly
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/// Target Optimization {
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// Return lower limit for number of blocks in a jump table.
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unsigned getMinimumJumpTableEntries() const override;
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// SX-Aurora VE's s/udiv is 5-9 times slower than multiply.
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bool isIntDivCheap(EVT, AttributeList) const override { return false; }
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// VE doesn't have rem.
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bool hasStandaloneRem(EVT) const override { return false; }
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// VE LDZ instruction returns 64 if the input is zero.
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bool isCheapToSpeculateCtlz() const override { return true; }
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// VE LDZ instruction is fast.
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bool isCtlzFast() const override { return true; }
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// VE has NND instruction.
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bool hasAndNot(SDValue Y) const override;
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/// } Target Optimization
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};
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} // namespace llvm
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#endif // VE_ISELLOWERING_H
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