97 lines
3.2 KiB
C++
97 lines
3.2 KiB
C++
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//===-- RISCVTargetTransformInfo.cpp - RISC-V specific TTI ----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVTargetTransformInfo.h"
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#include "MCTargetDesc/RISCVMatInt.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/CodeGen/TargetLowering.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscvtti"
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int RISCVTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty,
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TTI::TargetCostKind CostKind) {
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assert(Ty->isIntegerTy() &&
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"getIntImmCost can only estimate cost of materialising integers");
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// We have a Zero register, so 0 is always free.
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if (Imm == 0)
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return TTI::TCC_Free;
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// Otherwise, we check how many instructions it will take to materialise.
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const DataLayout &DL = getDataLayout();
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return RISCVMatInt::getIntMatCost(Imm, DL.getTypeSizeInBits(Ty),
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getST()->is64Bit());
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}
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int RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
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const APInt &Imm, Type *Ty,
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TTI::TargetCostKind CostKind,
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Instruction *Inst) {
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assert(Ty->isIntegerTy() &&
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"getIntImmCost can only estimate cost of materialising integers");
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// We have a Zero register, so 0 is always free.
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if (Imm == 0)
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return TTI::TCC_Free;
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// Some instructions in RISC-V can take a 12-bit immediate. Some of these are
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// commutative, in others the immediate comes from a specific argument index.
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bool Takes12BitImm = false;
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unsigned ImmArgIdx = ~0U;
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switch (Opcode) {
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case Instruction::GetElementPtr:
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// Never hoist any arguments to a GetElementPtr. CodeGenPrepare will
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// split up large offsets in GEP into better parts than ConstantHoisting
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// can.
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return TTI::TCC_Free;
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case Instruction::Add:
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case Instruction::And:
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case Instruction::Or:
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case Instruction::Xor:
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case Instruction::Mul:
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Takes12BitImm = true;
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break;
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case Instruction::Sub:
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case Instruction::Shl:
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case Instruction::LShr:
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case Instruction::AShr:
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Takes12BitImm = true;
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ImmArgIdx = 1;
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break;
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default:
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break;
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}
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if (Takes12BitImm) {
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// Check immediate is the correct argument...
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if (Instruction::isCommutative(Opcode) || Idx == ImmArgIdx) {
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// ... and fits into the 12-bit immediate.
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if (Imm.getMinSignedBits() <= 64 &&
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getTLI()->isLegalAddImmediate(Imm.getSExtValue())) {
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return TTI::TCC_Free;
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}
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}
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// Otherwise, use the full materialisation cost.
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return getIntImmCost(Imm, Ty, CostKind);
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}
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// By default, prevent hoisting.
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return TTI::TCC_Free;
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}
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int RISCVTTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
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const APInt &Imm, Type *Ty,
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TTI::TargetCostKind CostKind) {
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// Prevent hoisting in unknown cases.
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return TTI::TCC_Free;
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}
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