882 lines
29 KiB
C++
882 lines
29 KiB
C++
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//===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the RISCV implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVInstrInfo.h"
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#include "MCTargetDesc/RISCVMatInt.h"
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#include "RISCV.h"
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#include "RISCVSubtarget.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GEN_CHECK_COMPRESS_INSTR
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#include "RISCVGenCompressInstEmitter.inc"
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#define GET_INSTRINFO_CTOR_DTOR
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#include "RISCVGenInstrInfo.inc"
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RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI)
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: RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP),
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STI(STI) {}
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unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const {
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switch (MI.getOpcode()) {
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default:
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return 0;
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case RISCV::LB:
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case RISCV::LBU:
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case RISCV::LH:
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case RISCV::LHU:
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case RISCV::FLH:
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case RISCV::LW:
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case RISCV::FLW:
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case RISCV::LWU:
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case RISCV::LD:
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case RISCV::FLD:
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break;
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}
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if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
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MI.getOperand(2).getImm() == 0) {
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FrameIndex = MI.getOperand(1).getIndex();
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return MI.getOperand(0).getReg();
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}
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return 0;
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}
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unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const {
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switch (MI.getOpcode()) {
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default:
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return 0;
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case RISCV::SB:
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case RISCV::SH:
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case RISCV::SW:
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case RISCV::FSH:
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case RISCV::FSW:
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case RISCV::SD:
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case RISCV::FSD:
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break;
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}
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if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
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MI.getOperand(2).getImm() == 0) {
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FrameIndex = MI.getOperand(1).getIndex();
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return MI.getOperand(0).getReg();
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}
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return 0;
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}
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void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, MCRegister DstReg,
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MCRegister SrcReg, bool KillSrc) const {
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if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
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BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
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.addReg(SrcReg, getKillRegState(KillSrc))
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.addImm(0);
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return;
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}
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// FPR->FPR copies and VR->VR copies.
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unsigned Opc;
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bool IsScalableVector = false;
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if (RISCV::FPR16RegClass.contains(DstReg, SrcReg))
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Opc = RISCV::FSGNJ_H;
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else if (RISCV::FPR32RegClass.contains(DstReg, SrcReg))
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Opc = RISCV::FSGNJ_S;
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else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg))
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Opc = RISCV::FSGNJ_D;
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else if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {
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Opc = RISCV::PseudoVMV1R_V;
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IsScalableVector = true;
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} else if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) {
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Opc = RISCV::PseudoVMV2R_V;
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IsScalableVector = true;
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} else if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) {
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Opc = RISCV::PseudoVMV4R_V;
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IsScalableVector = true;
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} else if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) {
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Opc = RISCV::PseudoVMV8R_V;
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IsScalableVector = true;
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} else
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llvm_unreachable("Impossible reg-to-reg copy");
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if (IsScalableVector)
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BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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else
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BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
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.addReg(SrcReg, getKillRegState(KillSrc))
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.addReg(SrcReg, getKillRegState(KillSrc));
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}
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void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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Register SrcReg, bool IsKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end())
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DL = I->getDebugLoc();
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MachineFunction *MF = MBB.getParent();
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const MachineFrameInfo &MFI = MF->getFrameInfo();
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MachineMemOperand *MMO = MF->getMachineMemOperand(
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MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
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MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
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unsigned Opcode;
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if (RISCV::GPRRegClass.hasSubClassEq(RC))
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Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
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RISCV::SW : RISCV::SD;
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else if (RISCV::FPR16RegClass.hasSubClassEq(RC))
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Opcode = RISCV::FSH;
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else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
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Opcode = RISCV::FSW;
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else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
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Opcode = RISCV::FSD;
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else
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llvm_unreachable("Can't store this register to stack slot");
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BuildMI(MBB, I, DL, get(Opcode))
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.addReg(SrcReg, getKillRegState(IsKill))
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.addFrameIndex(FI)
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.addImm(0)
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.addMemOperand(MMO);
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}
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void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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Register DstReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end())
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DL = I->getDebugLoc();
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MachineFunction *MF = MBB.getParent();
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const MachineFrameInfo &MFI = MF->getFrameInfo();
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MachineMemOperand *MMO = MF->getMachineMemOperand(
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MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
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MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
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unsigned Opcode;
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if (RISCV::GPRRegClass.hasSubClassEq(RC))
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Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
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RISCV::LW : RISCV::LD;
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else if (RISCV::FPR16RegClass.hasSubClassEq(RC))
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Opcode = RISCV::FLH;
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else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
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Opcode = RISCV::FLW;
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else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
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Opcode = RISCV::FLD;
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else
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llvm_unreachable("Can't load this register from stack slot");
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BuildMI(MBB, I, DL, get(Opcode), DstReg)
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.addFrameIndex(FI)
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.addImm(0)
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.addMemOperand(MMO);
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}
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void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, Register DstReg, uint64_t Val,
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MachineInstr::MIFlag Flag) const {
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MachineFunction *MF = MBB.getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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bool IsRV64 = MF->getSubtarget<RISCVSubtarget>().is64Bit();
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Register SrcReg = RISCV::X0;
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Register Result = MRI.createVirtualRegister(&RISCV::GPRRegClass);
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unsigned Num = 0;
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if (!IsRV64 && !isInt<32>(Val))
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report_fatal_error("Should only materialize 32-bit constants for RV32");
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RISCVMatInt::InstSeq Seq;
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RISCVMatInt::generateInstSeq(Val, IsRV64, Seq);
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assert(Seq.size() > 0);
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for (RISCVMatInt::Inst &Inst : Seq) {
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// Write the final result to DstReg if it's the last instruction in the Seq.
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// Otherwise, write the result to the temp register.
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if (++Num == Seq.size())
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Result = DstReg;
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if (Inst.Opc == RISCV::LUI) {
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BuildMI(MBB, MBBI, DL, get(RISCV::LUI), Result)
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.addImm(Inst.Imm)
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.setMIFlag(Flag);
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} else {
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BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result)
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.addReg(SrcReg, RegState::Kill)
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.addImm(Inst.Imm)
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.setMIFlag(Flag);
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}
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// Only the first instruction has X0 as its source.
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SrcReg = Result;
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}
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}
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// The contents of values added to Cond are not examined outside of
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// RISCVInstrInfo, giving us flexibility in what to push to it. For RISCV, we
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// push BranchOpcode, Reg1, Reg2.
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static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
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SmallVectorImpl<MachineOperand> &Cond) {
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// Block ends with fall-through condbranch.
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assert(LastInst.getDesc().isConditionalBranch() &&
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"Unknown conditional branch");
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Target = LastInst.getOperand(2).getMBB();
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Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
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Cond.push_back(LastInst.getOperand(0));
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Cond.push_back(LastInst.getOperand(1));
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}
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static unsigned getOppositeBranchOpcode(int Opc) {
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switch (Opc) {
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default:
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llvm_unreachable("Unrecognized conditional branch");
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case RISCV::BEQ:
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return RISCV::BNE;
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case RISCV::BNE:
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return RISCV::BEQ;
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case RISCV::BLT:
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return RISCV::BGE;
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case RISCV::BGE:
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return RISCV::BLT;
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case RISCV::BLTU:
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return RISCV::BGEU;
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case RISCV::BGEU:
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return RISCV::BLTU;
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}
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}
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bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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TBB = FBB = nullptr;
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Cond.clear();
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
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if (I == MBB.end() || !isUnpredicatedTerminator(*I))
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return false;
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// Count the number of terminators and find the first unconditional or
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// indirect branch.
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MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
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int NumTerminators = 0;
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for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
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J++) {
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NumTerminators++;
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if (J->getDesc().isUnconditionalBranch() ||
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J->getDesc().isIndirectBranch()) {
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FirstUncondOrIndirectBr = J.getReverse();
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}
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}
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// If AllowModify is true, we can erase any terminators after
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// FirstUncondOrIndirectBR.
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if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
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while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
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std::next(FirstUncondOrIndirectBr)->eraseFromParent();
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NumTerminators--;
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}
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I = FirstUncondOrIndirectBr;
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}
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// We can't handle blocks that end in an indirect branch.
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if (I->getDesc().isIndirectBranch())
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return true;
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// We can't handle blocks with more than 2 terminators.
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if (NumTerminators > 2)
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return true;
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// Handle a single unconditional branch.
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if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
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TBB = getBranchDestBlock(*I);
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return false;
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}
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// Handle a single conditional branch.
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if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
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parseCondBranch(*I, TBB, Cond);
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return false;
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}
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// Handle a conditional branch followed by an unconditional branch.
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if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
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I->getDesc().isUnconditionalBranch()) {
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parseCondBranch(*std::prev(I), TBB, Cond);
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FBB = getBranchDestBlock(*I);
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return false;
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}
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// Otherwise, we can't handle this.
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return true;
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}
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unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved) const {
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if (BytesRemoved)
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*BytesRemoved = 0;
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MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
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if (I == MBB.end())
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||
|
|
return 0;
|
||
|
|
|
||
|
|
if (!I->getDesc().isUnconditionalBranch() &&
|
||
|
|
!I->getDesc().isConditionalBranch())
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
// Remove the branch.
|
||
|
|
if (BytesRemoved)
|
||
|
|
*BytesRemoved += getInstSizeInBytes(*I);
|
||
|
|
I->eraseFromParent();
|
||
|
|
|
||
|
|
I = MBB.end();
|
||
|
|
|
||
|
|
if (I == MBB.begin())
|
||
|
|
return 1;
|
||
|
|
--I;
|
||
|
|
if (!I->getDesc().isConditionalBranch())
|
||
|
|
return 1;
|
||
|
|
|
||
|
|
// Remove the branch.
|
||
|
|
if (BytesRemoved)
|
||
|
|
*BytesRemoved += getInstSizeInBytes(*I);
|
||
|
|
I->eraseFromParent();
|
||
|
|
return 2;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Inserts a branch into the end of the specific MachineBasicBlock, returning
|
||
|
|
// the number of instructions inserted.
|
||
|
|
unsigned RISCVInstrInfo::insertBranch(
|
||
|
|
MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
|
||
|
|
ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
|
||
|
|
if (BytesAdded)
|
||
|
|
*BytesAdded = 0;
|
||
|
|
|
||
|
|
// Shouldn't be a fall through.
|
||
|
|
assert(TBB && "insertBranch must not be told to insert a fallthrough");
|
||
|
|
assert((Cond.size() == 3 || Cond.size() == 0) &&
|
||
|
|
"RISCV branch conditions have two components!");
|
||
|
|
|
||
|
|
// Unconditional branch.
|
||
|
|
if (Cond.empty()) {
|
||
|
|
MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB);
|
||
|
|
if (BytesAdded)
|
||
|
|
*BytesAdded += getInstSizeInBytes(MI);
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Either a one or two-way conditional branch.
|
||
|
|
unsigned Opc = Cond[0].getImm();
|
||
|
|
MachineInstr &CondMI =
|
||
|
|
*BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
|
||
|
|
if (BytesAdded)
|
||
|
|
*BytesAdded += getInstSizeInBytes(CondMI);
|
||
|
|
|
||
|
|
// One-way conditional branch.
|
||
|
|
if (!FBB)
|
||
|
|
return 1;
|
||
|
|
|
||
|
|
// Two-way conditional branch.
|
||
|
|
MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB);
|
||
|
|
if (BytesAdded)
|
||
|
|
*BytesAdded += getInstSizeInBytes(MI);
|
||
|
|
return 2;
|
||
|
|
}
|
||
|
|
|
||
|
|
unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
|
||
|
|
MachineBasicBlock &DestBB,
|
||
|
|
const DebugLoc &DL,
|
||
|
|
int64_t BrOffset,
|
||
|
|
RegScavenger *RS) const {
|
||
|
|
assert(RS && "RegScavenger required for long branching");
|
||
|
|
assert(MBB.empty() &&
|
||
|
|
"new block should be inserted for expanding unconditional branch");
|
||
|
|
assert(MBB.pred_size() == 1);
|
||
|
|
|
||
|
|
MachineFunction *MF = MBB.getParent();
|
||
|
|
MachineRegisterInfo &MRI = MF->getRegInfo();
|
||
|
|
|
||
|
|
if (!isInt<32>(BrOffset))
|
||
|
|
report_fatal_error(
|
||
|
|
"Branch offsets outside of the signed 32-bit range not supported");
|
||
|
|
|
||
|
|
// FIXME: A virtual register must be used initially, as the register
|
||
|
|
// scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch
|
||
|
|
// uses the same workaround).
|
||
|
|
Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
|
||
|
|
auto II = MBB.end();
|
||
|
|
|
||
|
|
MachineInstr &MI = *BuildMI(MBB, II, DL, get(RISCV::PseudoJump))
|
||
|
|
.addReg(ScratchReg, RegState::Define | RegState::Dead)
|
||
|
|
.addMBB(&DestBB, RISCVII::MO_CALL);
|
||
|
|
|
||
|
|
RS->enterBasicBlockEnd(MBB);
|
||
|
|
unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass,
|
||
|
|
MI.getIterator(), false, 0);
|
||
|
|
MRI.replaceRegWith(ScratchReg, Scav);
|
||
|
|
MRI.clearVirtRegs();
|
||
|
|
RS->setRegUsed(Scav);
|
||
|
|
return 8;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool RISCVInstrInfo::reverseBranchCondition(
|
||
|
|
SmallVectorImpl<MachineOperand> &Cond) const {
|
||
|
|
assert((Cond.size() == 3) && "Invalid branch condition!");
|
||
|
|
Cond[0].setImm(getOppositeBranchOpcode(Cond[0].getImm()));
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
MachineBasicBlock *
|
||
|
|
RISCVInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
|
||
|
|
assert(MI.getDesc().isBranch() && "Unexpected opcode!");
|
||
|
|
// The branch target is always the last operand.
|
||
|
|
int NumOp = MI.getNumExplicitOperands();
|
||
|
|
return MI.getOperand(NumOp - 1).getMBB();
|
||
|
|
}
|
||
|
|
|
||
|
|
bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
|
||
|
|
int64_t BrOffset) const {
|
||
|
|
unsigned XLen = STI.getXLen();
|
||
|
|
// Ideally we could determine the supported branch offset from the
|
||
|
|
// RISCVII::FormMask, but this can't be used for Pseudo instructions like
|
||
|
|
// PseudoBR.
|
||
|
|
switch (BranchOp) {
|
||
|
|
default:
|
||
|
|
llvm_unreachable("Unexpected opcode!");
|
||
|
|
case RISCV::BEQ:
|
||
|
|
case RISCV::BNE:
|
||
|
|
case RISCV::BLT:
|
||
|
|
case RISCV::BGE:
|
||
|
|
case RISCV::BLTU:
|
||
|
|
case RISCV::BGEU:
|
||
|
|
return isIntN(13, BrOffset);
|
||
|
|
case RISCV::JAL:
|
||
|
|
case RISCV::PseudoBR:
|
||
|
|
return isIntN(21, BrOffset);
|
||
|
|
case RISCV::PseudoJump:
|
||
|
|
return isIntN(32, SignExtend64(BrOffset + 0x800, XLen));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
|
||
|
|
unsigned Opcode = MI.getOpcode();
|
||
|
|
|
||
|
|
switch (Opcode) {
|
||
|
|
default: {
|
||
|
|
if (MI.getParent() && MI.getParent()->getParent()) {
|
||
|
|
const auto MF = MI.getMF();
|
||
|
|
const auto &TM = static_cast<const RISCVTargetMachine &>(MF->getTarget());
|
||
|
|
const MCRegisterInfo &MRI = *TM.getMCRegisterInfo();
|
||
|
|
const MCSubtargetInfo &STI = *TM.getMCSubtargetInfo();
|
||
|
|
const RISCVSubtarget &ST = MF->getSubtarget<RISCVSubtarget>();
|
||
|
|
if (isCompressibleInst(MI, &ST, MRI, STI))
|
||
|
|
return 2;
|
||
|
|
}
|
||
|
|
return get(Opcode).getSize();
|
||
|
|
}
|
||
|
|
case TargetOpcode::EH_LABEL:
|
||
|
|
case TargetOpcode::IMPLICIT_DEF:
|
||
|
|
case TargetOpcode::KILL:
|
||
|
|
case TargetOpcode::DBG_VALUE:
|
||
|
|
return 0;
|
||
|
|
// These values are determined based on RISCVExpandAtomicPseudoInsts,
|
||
|
|
// RISCVExpandPseudoInsts and RISCVMCCodeEmitter, depending on where the
|
||
|
|
// pseudos are expanded.
|
||
|
|
case RISCV::PseudoCALLReg:
|
||
|
|
case RISCV::PseudoCALL:
|
||
|
|
case RISCV::PseudoJump:
|
||
|
|
case RISCV::PseudoTAIL:
|
||
|
|
case RISCV::PseudoLLA:
|
||
|
|
case RISCV::PseudoLA:
|
||
|
|
case RISCV::PseudoLA_TLS_IE:
|
||
|
|
case RISCV::PseudoLA_TLS_GD:
|
||
|
|
return 8;
|
||
|
|
case RISCV::PseudoAtomicLoadNand32:
|
||
|
|
case RISCV::PseudoAtomicLoadNand64:
|
||
|
|
return 20;
|
||
|
|
case RISCV::PseudoMaskedAtomicSwap32:
|
||
|
|
case RISCV::PseudoMaskedAtomicLoadAdd32:
|
||
|
|
case RISCV::PseudoMaskedAtomicLoadSub32:
|
||
|
|
return 28;
|
||
|
|
case RISCV::PseudoMaskedAtomicLoadNand32:
|
||
|
|
return 32;
|
||
|
|
case RISCV::PseudoMaskedAtomicLoadMax32:
|
||
|
|
case RISCV::PseudoMaskedAtomicLoadMin32:
|
||
|
|
return 44;
|
||
|
|
case RISCV::PseudoMaskedAtomicLoadUMax32:
|
||
|
|
case RISCV::PseudoMaskedAtomicLoadUMin32:
|
||
|
|
return 36;
|
||
|
|
case RISCV::PseudoCmpXchg32:
|
||
|
|
case RISCV::PseudoCmpXchg64:
|
||
|
|
return 16;
|
||
|
|
case RISCV::PseudoMaskedCmpXchg32:
|
||
|
|
return 32;
|
||
|
|
case TargetOpcode::INLINEASM:
|
||
|
|
case TargetOpcode::INLINEASM_BR: {
|
||
|
|
const MachineFunction &MF = *MI.getParent()->getParent();
|
||
|
|
const auto &TM = static_cast<const RISCVTargetMachine &>(MF.getTarget());
|
||
|
|
return getInlineAsmLength(MI.getOperand(0).getSymbolName(),
|
||
|
|
*TM.getMCAsmInfo());
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
|
||
|
|
const unsigned Opcode = MI.getOpcode();
|
||
|
|
switch (Opcode) {
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
case RISCV::FSGNJ_D:
|
||
|
|
case RISCV::FSGNJ_S:
|
||
|
|
// The canonical floating-point move is fsgnj rd, rs, rs.
|
||
|
|
return MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
|
||
|
|
MI.getOperand(1).getReg() == MI.getOperand(2).getReg();
|
||
|
|
case RISCV::ADDI:
|
||
|
|
case RISCV::ORI:
|
||
|
|
case RISCV::XORI:
|
||
|
|
return (MI.getOperand(1).isReg() &&
|
||
|
|
MI.getOperand(1).getReg() == RISCV::X0) ||
|
||
|
|
(MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0);
|
||
|
|
}
|
||
|
|
return MI.isAsCheapAsAMove();
|
||
|
|
}
|
||
|
|
|
||
|
|
Optional<DestSourcePair>
|
||
|
|
RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
|
||
|
|
if (MI.isMoveReg())
|
||
|
|
return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
|
||
|
|
switch (MI.getOpcode()) {
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
case RISCV::ADDI:
|
||
|
|
// Operand 1 can be a frameindex but callers expect registers
|
||
|
|
if (MI.getOperand(1).isReg() && MI.getOperand(2).isImm() &&
|
||
|
|
MI.getOperand(2).getImm() == 0)
|
||
|
|
return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
|
||
|
|
break;
|
||
|
|
case RISCV::FSGNJ_D:
|
||
|
|
case RISCV::FSGNJ_S:
|
||
|
|
// The canonical floating-point move is fsgnj rd, rs, rs.
|
||
|
|
if (MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
|
||
|
|
MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
|
||
|
|
return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
return None;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
|
||
|
|
StringRef &ErrInfo) const {
|
||
|
|
const MCInstrInfo *MCII = STI.getInstrInfo();
|
||
|
|
MCInstrDesc const &Desc = MCII->get(MI.getOpcode());
|
||
|
|
|
||
|
|
for (auto &OI : enumerate(Desc.operands())) {
|
||
|
|
unsigned OpType = OI.value().OperandType;
|
||
|
|
if (OpType >= RISCVOp::OPERAND_FIRST_RISCV_IMM &&
|
||
|
|
OpType <= RISCVOp::OPERAND_LAST_RISCV_IMM) {
|
||
|
|
const MachineOperand &MO = MI.getOperand(OI.index());
|
||
|
|
if (MO.isImm()) {
|
||
|
|
int64_t Imm = MO.getImm();
|
||
|
|
bool Ok;
|
||
|
|
switch (OpType) {
|
||
|
|
default:
|
||
|
|
llvm_unreachable("Unexpected operand type");
|
||
|
|
case RISCVOp::OPERAND_UIMM4:
|
||
|
|
Ok = isUInt<4>(Imm);
|
||
|
|
break;
|
||
|
|
case RISCVOp::OPERAND_UIMM5:
|
||
|
|
Ok = isUInt<5>(Imm);
|
||
|
|
break;
|
||
|
|
case RISCVOp::OPERAND_UIMM12:
|
||
|
|
Ok = isUInt<12>(Imm);
|
||
|
|
break;
|
||
|
|
case RISCVOp::OPERAND_SIMM12:
|
||
|
|
Ok = isInt<12>(Imm);
|
||
|
|
break;
|
||
|
|
case RISCVOp::OPERAND_UIMM20:
|
||
|
|
Ok = isUInt<20>(Imm);
|
||
|
|
break;
|
||
|
|
case RISCVOp::OPERAND_UIMMLOG2XLEN:
|
||
|
|
if (STI.getTargetTriple().isArch64Bit())
|
||
|
|
Ok = isUInt<6>(Imm);
|
||
|
|
else
|
||
|
|
Ok = isUInt<5>(Imm);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
if (!Ok) {
|
||
|
|
ErrInfo = "Invalid immediate";
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Return true if get the base operand, byte offset of an instruction and the
|
||
|
|
// memory width. Width is the size of memory that is being loaded/stored.
|
||
|
|
bool RISCVInstrInfo::getMemOperandWithOffsetWidth(
|
||
|
|
const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset,
|
||
|
|
unsigned &Width, const TargetRegisterInfo *TRI) const {
|
||
|
|
if (!LdSt.mayLoadOrStore())
|
||
|
|
return false;
|
||
|
|
|
||
|
|
// Here we assume the standard RISC-V ISA, which uses a base+offset
|
||
|
|
// addressing mode. You'll need to relax these conditions to support custom
|
||
|
|
// load/stores instructions.
|
||
|
|
if (LdSt.getNumExplicitOperands() != 3)
|
||
|
|
return false;
|
||
|
|
if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm())
|
||
|
|
return false;
|
||
|
|
|
||
|
|
if (!LdSt.hasOneMemOperand())
|
||
|
|
return false;
|
||
|
|
|
||
|
|
Width = (*LdSt.memoperands_begin())->getSize();
|
||
|
|
BaseReg = &LdSt.getOperand(1);
|
||
|
|
Offset = LdSt.getOperand(2).getImm();
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint(
|
||
|
|
const MachineInstr &MIa, const MachineInstr &MIb) const {
|
||
|
|
assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
|
||
|
|
assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
|
||
|
|
|
||
|
|
if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
|
||
|
|
MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
|
||
|
|
return false;
|
||
|
|
|
||
|
|
// Retrieve the base register, offset from the base register and width. Width
|
||
|
|
// is the size of memory that is being loaded/stored (e.g. 1, 2, 4). If
|
||
|
|
// base registers are identical, and the offset of a lower memory access +
|
||
|
|
// the width doesn't overlap the offset of a higher memory access,
|
||
|
|
// then the memory accesses are different.
|
||
|
|
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
|
||
|
|
const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
|
||
|
|
int64_t OffsetA = 0, OffsetB = 0;
|
||
|
|
unsigned int WidthA = 0, WidthB = 0;
|
||
|
|
if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
|
||
|
|
getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
|
||
|
|
if (BaseOpA->isIdenticalTo(*BaseOpB)) {
|
||
|
|
int LowOffset = std::min(OffsetA, OffsetB);
|
||
|
|
int HighOffset = std::max(OffsetA, OffsetB);
|
||
|
|
int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
|
||
|
|
if (LowOffset + LowWidth <= HighOffset)
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
std::pair<unsigned, unsigned>
|
||
|
|
RISCVInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
|
||
|
|
const unsigned Mask = RISCVII::MO_DIRECT_FLAG_MASK;
|
||
|
|
return std::make_pair(TF & Mask, TF & ~Mask);
|
||
|
|
}
|
||
|
|
|
||
|
|
ArrayRef<std::pair<unsigned, const char *>>
|
||
|
|
RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
|
||
|
|
using namespace RISCVII;
|
||
|
|
static const std::pair<unsigned, const char *> TargetFlags[] = {
|
||
|
|
{MO_CALL, "riscv-call"},
|
||
|
|
{MO_PLT, "riscv-plt"},
|
||
|
|
{MO_LO, "riscv-lo"},
|
||
|
|
{MO_HI, "riscv-hi"},
|
||
|
|
{MO_PCREL_LO, "riscv-pcrel-lo"},
|
||
|
|
{MO_PCREL_HI, "riscv-pcrel-hi"},
|
||
|
|
{MO_GOT_HI, "riscv-got-hi"},
|
||
|
|
{MO_TPREL_LO, "riscv-tprel-lo"},
|
||
|
|
{MO_TPREL_HI, "riscv-tprel-hi"},
|
||
|
|
{MO_TPREL_ADD, "riscv-tprel-add"},
|
||
|
|
{MO_TLS_GOT_HI, "riscv-tls-got-hi"},
|
||
|
|
{MO_TLS_GD_HI, "riscv-tls-gd-hi"}};
|
||
|
|
return makeArrayRef(TargetFlags);
|
||
|
|
}
|
||
|
|
bool RISCVInstrInfo::isFunctionSafeToOutlineFrom(
|
||
|
|
MachineFunction &MF, bool OutlineFromLinkOnceODRs) const {
|
||
|
|
const Function &F = MF.getFunction();
|
||
|
|
|
||
|
|
// Can F be deduplicated by the linker? If it can, don't outline from it.
|
||
|
|
if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
|
||
|
|
return false;
|
||
|
|
|
||
|
|
// Don't outline from functions with section markings; the program could
|
||
|
|
// expect that all the code is in the named section.
|
||
|
|
if (F.hasSection())
|
||
|
|
return false;
|
||
|
|
|
||
|
|
// It's safe to outline from MF.
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool RISCVInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
|
||
|
|
unsigned &Flags) const {
|
||
|
|
// More accurate safety checking is done in getOutliningCandidateInfo.
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Enum values indicating how an outlined call should be constructed.
|
||
|
|
enum MachineOutlinerConstructionID {
|
||
|
|
MachineOutlinerDefault
|
||
|
|
};
|
||
|
|
|
||
|
|
outliner::OutlinedFunction RISCVInstrInfo::getOutliningCandidateInfo(
|
||
|
|
std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
|
||
|
|
|
||
|
|
// First we need to filter out candidates where the X5 register (IE t0) can't
|
||
|
|
// be used to setup the function call.
|
||
|
|
auto CannotInsertCall = [](outliner::Candidate &C) {
|
||
|
|
const TargetRegisterInfo *TRI = C.getMF()->getSubtarget().getRegisterInfo();
|
||
|
|
|
||
|
|
C.initLRU(*TRI);
|
||
|
|
LiveRegUnits LRU = C.LRU;
|
||
|
|
return !LRU.available(RISCV::X5);
|
||
|
|
};
|
||
|
|
|
||
|
|
llvm::erase_if(RepeatedSequenceLocs, CannotInsertCall);
|
||
|
|
|
||
|
|
// If the sequence doesn't have enough candidates left, then we're done.
|
||
|
|
if (RepeatedSequenceLocs.size() < 2)
|
||
|
|
return outliner::OutlinedFunction();
|
||
|
|
|
||
|
|
unsigned SequenceSize = 0;
|
||
|
|
|
||
|
|
auto I = RepeatedSequenceLocs[0].front();
|
||
|
|
auto E = std::next(RepeatedSequenceLocs[0].back());
|
||
|
|
for (; I != E; ++I)
|
||
|
|
SequenceSize += getInstSizeInBytes(*I);
|
||
|
|
|
||
|
|
// call t0, function = 8 bytes.
|
||
|
|
unsigned CallOverhead = 8;
|
||
|
|
for (auto &C : RepeatedSequenceLocs)
|
||
|
|
C.setCallInfo(MachineOutlinerDefault, CallOverhead);
|
||
|
|
|
||
|
|
// jr t0 = 4 bytes, 2 bytes if compressed instructions are enabled.
|
||
|
|
unsigned FrameOverhead = 4;
|
||
|
|
if (RepeatedSequenceLocs[0].getMF()->getSubtarget()
|
||
|
|
.getFeatureBits()[RISCV::FeatureStdExtC])
|
||
|
|
FrameOverhead = 2;
|
||
|
|
|
||
|
|
return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
|
||
|
|
FrameOverhead, MachineOutlinerDefault);
|
||
|
|
}
|
||
|
|
|
||
|
|
outliner::InstrType
|
||
|
|
RISCVInstrInfo::getOutliningType(MachineBasicBlock::iterator &MBBI,
|
||
|
|
unsigned Flags) const {
|
||
|
|
MachineInstr &MI = *MBBI;
|
||
|
|
MachineBasicBlock *MBB = MI.getParent();
|
||
|
|
const TargetRegisterInfo *TRI =
|
||
|
|
MBB->getParent()->getSubtarget().getRegisterInfo();
|
||
|
|
|
||
|
|
// Positions generally can't safely be outlined.
|
||
|
|
if (MI.isPosition()) {
|
||
|
|
// We can manually strip out CFI instructions later.
|
||
|
|
if (MI.isCFIInstruction())
|
||
|
|
return outliner::InstrType::Invisible;
|
||
|
|
|
||
|
|
return outliner::InstrType::Illegal;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Don't trust the user to write safe inline assembly.
|
||
|
|
if (MI.isInlineAsm())
|
||
|
|
return outliner::InstrType::Illegal;
|
||
|
|
|
||
|
|
// We can't outline branches to other basic blocks.
|
||
|
|
if (MI.isTerminator() && !MBB->succ_empty())
|
||
|
|
return outliner::InstrType::Illegal;
|
||
|
|
|
||
|
|
// We need support for tail calls to outlined functions before return
|
||
|
|
// statements can be allowed.
|
||
|
|
if (MI.isReturn())
|
||
|
|
return outliner::InstrType::Illegal;
|
||
|
|
|
||
|
|
// Don't allow modifying the X5 register which we use for return addresses for
|
||
|
|
// these outlined functions.
|
||
|
|
if (MI.modifiesRegister(RISCV::X5, TRI) ||
|
||
|
|
MI.getDesc().hasImplicitDefOfPhysReg(RISCV::X5))
|
||
|
|
return outliner::InstrType::Illegal;
|
||
|
|
|
||
|
|
// Make sure the operands don't reference something unsafe.
|
||
|
|
for (const auto &MO : MI.operands())
|
||
|
|
if (MO.isMBB() || MO.isBlockAddress() || MO.isCPI())
|
||
|
|
return outliner::InstrType::Illegal;
|
||
|
|
|
||
|
|
// Don't allow instructions which won't be materialized to impact outlining
|
||
|
|
// analysis.
|
||
|
|
if (MI.isMetaInstruction())
|
||
|
|
return outliner::InstrType::Invisible;
|
||
|
|
|
||
|
|
return outliner::InstrType::Legal;
|
||
|
|
}
|
||
|
|
|
||
|
|
void RISCVInstrInfo::buildOutlinedFrame(
|
||
|
|
MachineBasicBlock &MBB, MachineFunction &MF,
|
||
|
|
const outliner::OutlinedFunction &OF) const {
|
||
|
|
|
||
|
|
// Strip out any CFI instructions
|
||
|
|
bool Changed = true;
|
||
|
|
while (Changed) {
|
||
|
|
Changed = false;
|
||
|
|
auto I = MBB.begin();
|
||
|
|
auto E = MBB.end();
|
||
|
|
for (; I != E; ++I) {
|
||
|
|
if (I->isCFIInstruction()) {
|
||
|
|
I->removeFromParent();
|
||
|
|
Changed = true;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
MBB.addLiveIn(RISCV::X5);
|
||
|
|
|
||
|
|
// Add in a return instruction to the end of the outlined frame.
|
||
|
|
MBB.insert(MBB.end(), BuildMI(MF, DebugLoc(), get(RISCV::JALR))
|
||
|
|
.addReg(RISCV::X0, RegState::Define)
|
||
|
|
.addReg(RISCV::X5)
|
||
|
|
.addImm(0));
|
||
|
|
}
|
||
|
|
|
||
|
|
MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(
|
||
|
|
Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It,
|
||
|
|
MachineFunction &MF, const outliner::Candidate &C) const {
|
||
|
|
|
||
|
|
// Add in a call instruction to the outlined function at the given location.
|
||
|
|
It = MBB.insert(It,
|
||
|
|
BuildMI(MF, DebugLoc(), get(RISCV::PseudoCALLReg), RISCV::X5)
|
||
|
|
.addGlobalAddress(M.getNamedValue(MF.getName()), 0,
|
||
|
|
RISCVII::MO_CALL));
|
||
|
|
return It;
|
||
|
|
}
|