77 lines
2.5 KiB
C
77 lines
2.5 KiB
C
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//===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISCV ------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the RISCV target.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
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#define LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
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#include "RISCV.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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// RISCV-specific code to select RISCV machine instructions for
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// SelectionDAG operations.
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namespace llvm {
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class RISCVDAGToDAGISel : public SelectionDAGISel {
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const RISCVSubtarget *Subtarget = nullptr;
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public:
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explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine)
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: SelectionDAGISel(TargetMachine) {}
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StringRef getPassName() const override {
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return "RISCV DAG->DAG Pattern Instruction Selection";
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}
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bool runOnMachineFunction(MachineFunction &MF) override {
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Subtarget = &MF.getSubtarget<RISCVSubtarget>();
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return SelectionDAGISel::runOnMachineFunction(MF);
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}
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void PostprocessISelDAG() override;
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void Select(SDNode *Node) override;
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bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
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std::vector<SDValue> &OutOps) override;
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bool SelectAddrFI(SDValue Addr, SDValue &Base);
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bool MatchSRLIW(SDNode *N) const;
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bool MatchSLLIUW(SDNode *N) const;
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bool selectVLOp(SDValue N, SDValue &VL);
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bool selectVSplat(SDValue N, SDValue &SplatVal);
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bool selectVSplatSimm5(SDValue N, SDValue &SplatVal);
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bool selectVSplatUimm5(SDValue N, SDValue &SplatVal);
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void selectVLSEG(SDNode *Node, unsigned IntNo, bool IsStrided);
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void selectVLSEGMask(SDNode *Node, unsigned IntNo, bool IsStrided);
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void selectVLSEGFF(SDNode *Node);
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void selectVLSEGFFMask(SDNode *Node);
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void selectVLXSEG(SDNode *Node, unsigned IntNo);
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void selectVLXSEGMask(SDNode *Node, unsigned IntNo);
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void selectVSSEG(SDNode *Node, unsigned IntNo, bool IsStrided);
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void selectVSSEGMask(SDNode *Node, unsigned IntNo, bool IsStrided);
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void selectVSXSEG(SDNode *Node, unsigned IntNo);
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void selectVSXSEGMask(SDNode *Node, unsigned IntNo);
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// Include the pieces autogenerated from the target description.
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#include "RISCVGenDAGISel.inc"
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private:
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void doPeepholeLoadStoreADDI();
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};
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}
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#endif
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