44 lines
1.6 KiB
C
44 lines
1.6 KiB
C
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//===- RISCVMatInt.h - Immediate materialisation ---------------*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_MATINT_H
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#define LLVM_LIB_TARGET_RISCV_MATINT_H
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#include "llvm/ADT/SmallVector.h"
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#include <cstdint>
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namespace llvm {
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class APInt;
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namespace RISCVMatInt {
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struct Inst {
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unsigned Opc;
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int64_t Imm;
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Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {}
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};
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using InstSeq = SmallVector<Inst, 8>;
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// Helper to generate an instruction sequence that will materialise the given
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// immediate value into a register. A sequence of instructions represented by
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// a simple struct produced rather than directly emitting the instructions in
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// order to allow this helper to be used from both the MC layer and during
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// instruction selection.
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void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res);
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// Helper to estimate the number of instructions required to materialise the
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// given immediate value into a register. This estimate does not account for
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// `Val` possibly fitting into an immediate, and so may over-estimate.
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//
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// This will attempt to produce instructions to materialise `Val` as an
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// `Size`-bit immediate. `IsRV64` should match the target architecture.
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int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64);
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} // namespace RISCVMatInt
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} // namespace llvm
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#endif
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