280 lines
17 KiB
TableGen
280 lines
17 KiB
TableGen
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//===-- PPCScheduleE500.td - e500 Scheduling Defs ------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the Freescale e500 32-bit
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// Power processor.
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//
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// All information is derived from the "e500 Core Reference Manual",
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// Freescale Document Number E500MCRM, Rev. 1, 03/2012.
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//
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//===----------------------------------------------------------------------===//
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// Relevant functional units in the Freescale e500 core:
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//
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// * Decode & Dispatch
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// Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
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// queues (GIQx) or Branch issue queue (BIQ).
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def E500_DIS0 : FuncUnit; // Dispatch stage - insn 1
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def E500_DIS1 : FuncUnit; // Dispatch stage - insn 2
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// * Execute
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// 6 pipelined execution units: SU0, SU1, BU, LSU, MU.
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// Some instructions can only execute in SU0 but not SU1.
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def E500_SU0 : FuncUnit; // Simple unit 0
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def E500_SU1 : FuncUnit; // Simple unit 1
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def E500_BU : FuncUnit; // Branch unit
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def E500_MU : FuncUnit; // MU pipeline
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def E500_LSU_0 : FuncUnit; // LSU pipeline
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def E500_GPR_Bypass : Bypass;
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def E500_CR_Bypass : Bypass;
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def E500_DivBypass : Bypass;
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def PPCE500Itineraries : ProcessorItineraries<
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[E500_DIS0, E500_DIS1, E500_SU0, E500_SU1, E500_BU,
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E500_MU, E500_LSU_0],
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[E500_CR_Bypass, E500_GPR_Bypass, E500_DivBypass], [
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InstrItinData<IIC_IntSimple, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1]>],
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[4, 1, 1], // Latency = 1
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[E500_GPR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1]>],
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[4, 1, 1], // Latency = 1
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[E500_GPR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_IntISEL, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1]>],
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[4, 1, 1, 1], // Latency = 1
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[E500_GPR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass,
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E500_CR_Bypass]>,
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InstrItinData<IIC_IntCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1]>],
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[5, 1, 1], // Latency = 1 or 2
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[E500_CR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_IntDivW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_MU], 0>,
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InstrStage<14, [E500_MU]>],
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[17, 1, 1], // Latency=4..35, Repeat= 4..35
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[E500_GPR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<4, [E500_MU]>],
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[7, 1, 1], // Latency = 4, Repeat rate = 1
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[E500_GPR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<4, [E500_MU]>],
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[7, 1, 1], // Latency = 4, Repeat rate = 1
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[E500_GPR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<4, [E500_MU]>],
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[7, 1, 1], // Latency = 4, Repeat rate = 1
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[E500_GPR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_IntRotate, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1]>],
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[4, 1, 1], // Latency = 1
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[E500_GPR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_IntShift, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1]>],
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[4, 1, 1], // Latency = 1
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[E500_GPR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<2, [E500_SU0]>],
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[5, 1], // Latency = 2, Repeat rate = 2
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_BrB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_BU]>],
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[4, 1], // Latency = 1
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[NoBypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_BrCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_BU]>],
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[4, 1, 1], // Latency = 1
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[E500_CR_Bypass,
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E500_CR_Bypass, E500_CR_Bypass]>,
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InstrItinData<IIC_BrMCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_BU]>],
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[4, 1], // Latency = 1
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[E500_CR_Bypass, E500_CR_Bypass]>,
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InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1]>],
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[4, 1, 1], // Latency = 1
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[E500_CR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3, Repeat rate = 1
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStLoad, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[E500_GPR_Bypass, E500_GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[E500_GPR_Bypass, E500_GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<IIC_LdStStore, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[NoBypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStSTU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[NoBypass, E500_GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<IIC_LdStSTUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[NoBypass, E500_GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<IIC_LdStICBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[NoBypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[7, 1], // Latency = r+3
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[NoBypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<3, [E500_LSU_0]>],
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[6, 1, 1], // Latency = 3, Repeat rate = 3
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[E500_GPR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[NoBypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStSync, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0]>]>,
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InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<4, [E500_SU0]>],
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[7, 1],
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<2, [E500_SU0, E500_SU1]>],
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[5, 1], // Latency = 2, Repeat rate = 4
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0]>],
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[5, 1],
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[NoBypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0], 0>]>,
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InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<5, [E500_SU0]>],
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[8, 1],
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[E500_GPR_Bypass, E500_CR_Bypass]>,
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InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<5, [E500_SU0]>],
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[8, 1],
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[E500_GPR_Bypass, E500_CR_Bypass]>,
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InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<4, [E500_SU0]>],
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[7, 1], // Latency = 4, Repeat rate = 4
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<4, [E500_SU0]>],
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[7, 1], // Latency = 4, Repeat rate = 4
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1]>],
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[4, 1], // Latency = 1, Repeat rate = 1
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[E500_GPR_Bypass, E500_CR_Bypass]>,
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InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0]>],
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[4, 1], // Latency = 1, Repeat rate = 1
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[E500_CR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<4, [E500_SU0]>],
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[7, 1], // Latency = 4, Repeat rate = 4
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[NoBypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1]>],
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[4, 1], // Latency = 1, Repeat rate = 1
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[E500_CR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0]>],
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[4, 1],
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[NoBypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_FPDGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<6, [E500_MU]>],
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[9, 1, 1], // Latency = 6, Repeat rate = 1
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[NoBypass]>,
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InstrItinData<IIC_FPSGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<4, [E500_MU]>],
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[7, 1, 1], // Latency = 4, Repeat rate = 1
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[NoBypass]>,
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InstrItinData<IIC_FPDivD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<32, [E500_MU]>],
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[35, 1, 1], // Latency = 32, Repeat rate = 32
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[E500_DivBypass]>,
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InstrItinData<IIC_FPDivS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<29, [E500_MU]>],
|
||
|
|
[32, 1, 1], // Latency = 29, Repeat rate = 29
|
||
|
|
[E500_DivBypass]>,
|
||
|
|
InstrItinData<IIC_VecGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||
|
|
InstrStage<1, [E500_SU0]>],
|
||
|
|
[4, 1, 1], // Latency = 1, Repeat rate = 1
|
||
|
|
[NoBypass]>,
|
||
|
|
InstrItinData<IIC_VecComplex, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||
|
|
InstrStage<4, [E500_MU]>],
|
||
|
|
[7, 1, 1], // Latency = 4, Repeat rate = 1
|
||
|
|
[NoBypass]>
|
||
|
|
]>;
|
||
|
|
|
||
|
|
// ===---------------------------------------------------------------------===//
|
||
|
|
// e500 machine model for scheduling and other instruction cost heuristics.
|
||
|
|
|
||
|
|
def PPCE500Model : SchedMachineModel {
|
||
|
|
let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
|
||
|
|
let LoadLatency = 5; // Optimistic load latency assuming bypass.
|
||
|
|
// This is overriden by OperandCycles if the
|
||
|
|
// Itineraries are queried instead.
|
||
|
|
|
||
|
|
let CompleteModel = 0;
|
||
|
|
|
||
|
|
let Itineraries = PPCE500Itineraries;
|
||
|
|
}
|