563 lines
22 KiB
C++
563 lines
22 KiB
C++
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//===--------- PPCPreEmitPeephole.cpp - Late peephole optimizations -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// A pre-emit peephole for catching opportunities introduced by late passes such
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// as MachineBlockPlacement.
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//
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//===----------------------------------------------------------------------===//
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#include "PPC.h"
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#include "PPCInstrInfo.h"
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#include "PPCSubtarget.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "ppc-pre-emit-peephole"
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STATISTIC(NumRRConvertedInPreEmit,
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"Number of r+r instructions converted to r+i in pre-emit peephole");
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STATISTIC(NumRemovedInPreEmit,
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"Number of instructions deleted in pre-emit peephole");
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STATISTIC(NumberOfSelfCopies,
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"Number of self copy instructions eliminated");
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STATISTIC(NumFrameOffFoldInPreEmit,
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"Number of folding frame offset by using r+r in pre-emit peephole");
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static cl::opt<bool>
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EnablePCRelLinkerOpt("ppc-pcrel-linker-opt", cl::Hidden, cl::init(true),
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cl::desc("enable PC Relative linker optimization"));
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static cl::opt<bool>
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RunPreEmitPeephole("ppc-late-peephole", cl::Hidden, cl::init(true),
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cl::desc("Run pre-emit peephole optimizations."));
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namespace {
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static bool hasPCRelativeForm(MachineInstr &Use) {
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switch (Use.getOpcode()) {
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default:
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return false;
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case PPC::LBZ:
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case PPC::LBZ8:
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case PPC::LHA:
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case PPC::LHA8:
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case PPC::LHZ:
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case PPC::LHZ8:
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case PPC::LWZ:
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case PPC::LWZ8:
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case PPC::STB:
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case PPC::STB8:
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case PPC::STH:
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case PPC::STH8:
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case PPC::STW:
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case PPC::STW8:
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case PPC::LD:
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case PPC::STD:
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case PPC::LWA:
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case PPC::LXSD:
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case PPC::LXSSP:
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case PPC::LXV:
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case PPC::STXSD:
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case PPC::STXSSP:
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case PPC::STXV:
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case PPC::LFD:
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case PPC::LFS:
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case PPC::STFD:
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case PPC::STFS:
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case PPC::DFLOADf32:
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case PPC::DFLOADf64:
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case PPC::DFSTOREf32:
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case PPC::DFSTOREf64:
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return true;
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}
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}
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class PPCPreEmitPeephole : public MachineFunctionPass {
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public:
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static char ID;
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PPCPreEmitPeephole() : MachineFunctionPass(ID) {
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initializePPCPreEmitPeepholePass(*PassRegistry::getPassRegistry());
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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// This function removes any redundant load immediates. It has two level
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// loops - The outer loop finds the load immediates BBI that could be used
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// to replace following redundancy. The inner loop scans instructions that
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// after BBI to find redundancy and update kill/dead flags accordingly. If
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// AfterBBI is the same as BBI, it is redundant, otherwise any instructions
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// that modify the def register of BBI would break the scanning.
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// DeadOrKillToUnset is a pointer to the previous operand that had the
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// kill/dead flag set. It keeps track of the def register of BBI, the use
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// registers of AfterBBIs and the def registers of AfterBBIs.
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bool removeRedundantLIs(MachineBasicBlock &MBB,
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const TargetRegisterInfo *TRI) {
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LLVM_DEBUG(dbgs() << "Remove redundant load immediates from MBB:\n";
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MBB.dump(); dbgs() << "\n");
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DenseSet<MachineInstr *> InstrsToErase;
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for (auto BBI = MBB.instr_begin(); BBI != MBB.instr_end(); ++BBI) {
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// Skip load immediate that is marked to be erased later because it
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// cannot be used to replace any other instructions.
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if (InstrsToErase.contains(&*BBI))
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continue;
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// Skip non-load immediate.
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unsigned Opc = BBI->getOpcode();
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if (Opc != PPC::LI && Opc != PPC::LI8 && Opc != PPC::LIS &&
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Opc != PPC::LIS8)
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continue;
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// Skip load immediate, where the operand is a relocation (e.g., $r3 =
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// LI target-flags(ppc-lo) %const.0).
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if (!BBI->getOperand(1).isImm())
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continue;
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assert(BBI->getOperand(0).isReg() &&
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"Expected a register for the first operand");
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LLVM_DEBUG(dbgs() << "Scanning after load immediate: "; BBI->dump(););
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Register Reg = BBI->getOperand(0).getReg();
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int64_t Imm = BBI->getOperand(1).getImm();
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MachineOperand *DeadOrKillToUnset = nullptr;
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if (BBI->getOperand(0).isDead()) {
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DeadOrKillToUnset = &BBI->getOperand(0);
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LLVM_DEBUG(dbgs() << " Kill flag of " << *DeadOrKillToUnset
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<< " from load immediate " << *BBI
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<< " is a unsetting candidate\n");
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}
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// This loop scans instructions after BBI to see if there is any
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// redundant load immediate.
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for (auto AfterBBI = std::next(BBI); AfterBBI != MBB.instr_end();
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++AfterBBI) {
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// Track the operand that kill Reg. We would unset the kill flag of
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// the operand if there is a following redundant load immediate.
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int KillIdx = AfterBBI->findRegisterUseOperandIdx(Reg, true, TRI);
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// We can't just clear implicit kills, so if we encounter one, stop
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// looking further.
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if (KillIdx != -1 && AfterBBI->getOperand(KillIdx).isImplicit()) {
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LLVM_DEBUG(dbgs()
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<< "Encountered an implicit kill, cannot proceed: ");
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LLVM_DEBUG(AfterBBI->dump());
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break;
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}
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if (KillIdx != -1) {
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assert(!DeadOrKillToUnset && "Shouldn't kill same register twice");
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DeadOrKillToUnset = &AfterBBI->getOperand(KillIdx);
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LLVM_DEBUG(dbgs()
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<< " Kill flag of " << *DeadOrKillToUnset << " from "
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<< *AfterBBI << " is a unsetting candidate\n");
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}
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if (!AfterBBI->modifiesRegister(Reg, TRI))
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continue;
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// Finish scanning because Reg is overwritten by a non-load
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// instruction.
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if (AfterBBI->getOpcode() != Opc)
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break;
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assert(AfterBBI->getOperand(0).isReg() &&
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"Expected a register for the first operand");
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// Finish scanning because Reg is overwritten by a relocation or a
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// different value.
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if (!AfterBBI->getOperand(1).isImm() ||
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AfterBBI->getOperand(1).getImm() != Imm)
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break;
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// It loads same immediate value to the same Reg, which is redundant.
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// We would unset kill flag in previous Reg usage to extend live range
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// of Reg first, then remove the redundancy.
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if (DeadOrKillToUnset) {
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LLVM_DEBUG(dbgs()
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<< " Unset dead/kill flag of " << *DeadOrKillToUnset
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<< " from " << *DeadOrKillToUnset->getParent());
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if (DeadOrKillToUnset->isDef())
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DeadOrKillToUnset->setIsDead(false);
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else
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DeadOrKillToUnset->setIsKill(false);
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}
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DeadOrKillToUnset =
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AfterBBI->findRegisterDefOperand(Reg, true, true, TRI);
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if (DeadOrKillToUnset)
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LLVM_DEBUG(dbgs()
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<< " Dead flag of " << *DeadOrKillToUnset << " from "
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<< *AfterBBI << " is a unsetting candidate\n");
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InstrsToErase.insert(&*AfterBBI);
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LLVM_DEBUG(dbgs() << " Remove redundant load immediate: ";
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AfterBBI->dump());
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}
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}
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for (MachineInstr *MI : InstrsToErase) {
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MI->eraseFromParent();
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}
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NumRemovedInPreEmit += InstrsToErase.size();
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return !InstrsToErase.empty();
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}
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// Check if this instruction is a PLDpc that is part of a GOT indirect
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// access.
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bool isGOTPLDpc(MachineInstr &Instr) {
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if (Instr.getOpcode() != PPC::PLDpc)
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return false;
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// The result must be a register.
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const MachineOperand &LoadedAddressReg = Instr.getOperand(0);
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if (!LoadedAddressReg.isReg())
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return false;
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// Make sure that this is a global symbol.
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const MachineOperand &SymbolOp = Instr.getOperand(1);
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if (!SymbolOp.isGlobal())
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return false;
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// Finally return true only if the GOT flag is present.
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return (SymbolOp.getTargetFlags() & PPCII::MO_GOT_FLAG);
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}
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bool addLinkerOpt(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI) {
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MachineFunction *MF = MBB.getParent();
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// If the linker opt is disabled then just return.
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if (!EnablePCRelLinkerOpt)
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return false;
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// Add this linker opt only if we are using PC Relative memops.
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if (!MF->getSubtarget<PPCSubtarget>().isUsingPCRelativeCalls())
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return false;
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// Struct to keep track of one def/use pair for a GOT indirect access.
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struct GOTDefUsePair {
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MachineBasicBlock::iterator DefInst;
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MachineBasicBlock::iterator UseInst;
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Register DefReg;
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Register UseReg;
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bool StillValid;
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};
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// Vector of def/ues pairs in this basic block.
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SmallVector<GOTDefUsePair, 4> CandPairs;
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SmallVector<GOTDefUsePair, 4> ValidPairs;
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bool MadeChange = false;
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// Run through all of the instructions in the basic block and try to
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// collect potential pairs of GOT indirect access instructions.
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for (auto BBI = MBB.instr_begin(); BBI != MBB.instr_end(); ++BBI) {
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// Look for the initial GOT indirect load.
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if (isGOTPLDpc(*BBI)) {
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GOTDefUsePair CurrentPair{BBI, MachineBasicBlock::iterator(),
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BBI->getOperand(0).getReg(),
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PPC::NoRegister, true};
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CandPairs.push_back(CurrentPair);
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continue;
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}
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// We haven't encountered any new PLD instructions, nothing to check.
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if (CandPairs.empty())
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continue;
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// Run through the candidate pairs and see if any of the registers
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// defined in the PLD instructions are used by this instruction.
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// Note: the size of CandPairs can change in the loop.
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for (unsigned Idx = 0; Idx < CandPairs.size(); Idx++) {
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GOTDefUsePair &Pair = CandPairs[Idx];
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// The instruction does not use or modify this PLD's def reg,
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// ignore it.
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if (!BBI->readsRegister(Pair.DefReg, TRI) &&
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!BBI->modifiesRegister(Pair.DefReg, TRI))
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continue;
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// The use needs to be used in the address compuation and not
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// as the register being stored for a store.
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const MachineOperand *UseOp =
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hasPCRelativeForm(*BBI) ? &BBI->getOperand(2) : nullptr;
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// Check for a valid use.
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if (UseOp && UseOp->isReg() && UseOp->getReg() == Pair.DefReg &&
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UseOp->isUse() && UseOp->isKill()) {
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Pair.UseInst = BBI;
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Pair.UseReg = BBI->getOperand(0).getReg();
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ValidPairs.push_back(Pair);
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}
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CandPairs.erase(CandPairs.begin() + Idx);
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}
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}
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// Go through all of the pairs and check for any more valid uses.
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for (auto Pair = ValidPairs.begin(); Pair != ValidPairs.end(); Pair++) {
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// We shouldn't be here if we don't have a valid pair.
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assert(Pair->UseInst.isValid() && Pair->StillValid &&
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"Kept an invalid def/use pair for GOT PCRel opt");
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// We have found a potential pair. Search through the instructions
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// between the def and the use to see if it is valid to mark this as a
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// linker opt.
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MachineBasicBlock::iterator BBI = Pair->DefInst;
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++BBI;
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for (; BBI != Pair->UseInst; ++BBI) {
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if (BBI->readsRegister(Pair->UseReg, TRI) ||
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BBI->modifiesRegister(Pair->UseReg, TRI)) {
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Pair->StillValid = false;
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break;
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}
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}
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if (!Pair->StillValid)
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continue;
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// The load/store instruction that uses the address from the PLD will
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// either use a register (for a store) or define a register (for the
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// load). That register will be added as an implicit def to the PLD
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// and as an implicit use on the second memory op. This is a precaution
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// to prevent future passes from using that register between the two
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// instructions.
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MachineOperand ImplDef =
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MachineOperand::CreateReg(Pair->UseReg, true, true);
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MachineOperand ImplUse =
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MachineOperand::CreateReg(Pair->UseReg, false, true);
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Pair->DefInst->addOperand(ImplDef);
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Pair->UseInst->addOperand(ImplUse);
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// Create the symbol.
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MCContext &Context = MF->getContext();
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MCSymbol *Symbol = Context.createNamedTempSymbol("pcrel");
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MachineOperand PCRelLabel =
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MachineOperand::CreateMCSymbol(Symbol, PPCII::MO_PCREL_OPT_FLAG);
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Pair->DefInst->addOperand(*MF, PCRelLabel);
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Pair->UseInst->addOperand(*MF, PCRelLabel);
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MadeChange |= true;
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}
|
||
|
|
return MadeChange;
|
||
|
|
}
|
||
|
|
|
||
|
|
// This function removes redundant pairs of accumulator prime/unprime
|
||
|
|
// instructions. In some situations, it's possible the compiler inserts an
|
||
|
|
// accumulator prime instruction followed by an unprime instruction (e.g.
|
||
|
|
// when we store an accumulator after restoring it from a spill). If the
|
||
|
|
// accumulator is not used between the two, they can be removed. This
|
||
|
|
// function removes these redundant pairs from basic blocks.
|
||
|
|
// The algorithm is quite straightforward - every time we encounter a prime
|
||
|
|
// instruction, the primed register is added to a candidate set. Any use
|
||
|
|
// other than a prime removes the candidate from the set and any de-prime
|
||
|
|
// of a current candidate marks both the prime and de-prime for removal.
|
||
|
|
// This way we ensure we only remove prime/de-prime *pairs* with no
|
||
|
|
// intervening uses.
|
||
|
|
bool removeAccPrimeUnprime(MachineBasicBlock &MBB) {
|
||
|
|
DenseSet<MachineInstr *> InstrsToErase;
|
||
|
|
// Initially, none of the acc registers are candidates.
|
||
|
|
SmallVector<MachineInstr *, 8> Candidates(
|
||
|
|
PPC::UACCRCRegClass.getNumRegs(), nullptr);
|
||
|
|
|
||
|
|
for (MachineInstr &BBI : MBB.instrs()) {
|
||
|
|
unsigned Opc = BBI.getOpcode();
|
||
|
|
// If we are visiting a xxmtacc instruction, we add it and its operand
|
||
|
|
// register to the candidate set.
|
||
|
|
if (Opc == PPC::XXMTACC) {
|
||
|
|
Register Acc = BBI.getOperand(0).getReg();
|
||
|
|
assert(PPC::ACCRCRegClass.contains(Acc) &&
|
||
|
|
"Unexpected register for XXMTACC");
|
||
|
|
Candidates[Acc - PPC::ACC0] = &BBI;
|
||
|
|
}
|
||
|
|
// If we are visiting a xxmfacc instruction and its operand register is
|
||
|
|
// in the candidate set, we mark the two instructions for removal.
|
||
|
|
else if (Opc == PPC::XXMFACC) {
|
||
|
|
Register Acc = BBI.getOperand(0).getReg();
|
||
|
|
assert(PPC::ACCRCRegClass.contains(Acc) &&
|
||
|
|
"Unexpected register for XXMFACC");
|
||
|
|
if (!Candidates[Acc - PPC::ACC0])
|
||
|
|
continue;
|
||
|
|
InstrsToErase.insert(&BBI);
|
||
|
|
InstrsToErase.insert(Candidates[Acc - PPC::ACC0]);
|
||
|
|
}
|
||
|
|
// If we are visiting an instruction using an accumulator register
|
||
|
|
// as operand, we remove it from the candidate set.
|
||
|
|
else {
|
||
|
|
for (MachineOperand &Operand : BBI.operands()) {
|
||
|
|
if (!Operand.isReg())
|
||
|
|
continue;
|
||
|
|
Register Reg = Operand.getReg();
|
||
|
|
if (PPC::ACCRCRegClass.contains(Reg))
|
||
|
|
Candidates[Reg - PPC::ACC0] = nullptr;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
for (MachineInstr *MI : InstrsToErase)
|
||
|
|
MI->eraseFromParent();
|
||
|
|
NumRemovedInPreEmit += InstrsToErase.size();
|
||
|
|
return !InstrsToErase.empty();
|
||
|
|
}
|
||
|
|
|
||
|
|
bool runOnMachineFunction(MachineFunction &MF) override {
|
||
|
|
if (skipFunction(MF.getFunction()) || !RunPreEmitPeephole) {
|
||
|
|
// Remove UNENCODED_NOP even when this pass is disabled.
|
||
|
|
// This needs to be done unconditionally so we don't emit zeros
|
||
|
|
// in the instruction stream.
|
||
|
|
SmallVector<MachineInstr *, 4> InstrsToErase;
|
||
|
|
for (MachineBasicBlock &MBB : MF)
|
||
|
|
for (MachineInstr &MI : MBB)
|
||
|
|
if (MI.getOpcode() == PPC::UNENCODED_NOP)
|
||
|
|
InstrsToErase.push_back(&MI);
|
||
|
|
for (MachineInstr *MI : InstrsToErase)
|
||
|
|
MI->eraseFromParent();
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
bool Changed = false;
|
||
|
|
const PPCInstrInfo *TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo();
|
||
|
|
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
|
||
|
|
SmallVector<MachineInstr *, 4> InstrsToErase;
|
||
|
|
for (MachineBasicBlock &MBB : MF) {
|
||
|
|
Changed |= removeRedundantLIs(MBB, TRI);
|
||
|
|
Changed |= addLinkerOpt(MBB, TRI);
|
||
|
|
Changed |= removeAccPrimeUnprime(MBB);
|
||
|
|
for (MachineInstr &MI : MBB) {
|
||
|
|
unsigned Opc = MI.getOpcode();
|
||
|
|
if (Opc == PPC::UNENCODED_NOP) {
|
||
|
|
InstrsToErase.push_back(&MI);
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
// Detect self copies - these can result from running AADB.
|
||
|
|
if (PPCInstrInfo::isSameClassPhysRegCopy(Opc)) {
|
||
|
|
const MCInstrDesc &MCID = TII->get(Opc);
|
||
|
|
if (MCID.getNumOperands() == 3 &&
|
||
|
|
MI.getOperand(0).getReg() == MI.getOperand(1).getReg() &&
|
||
|
|
MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) {
|
||
|
|
NumberOfSelfCopies++;
|
||
|
|
LLVM_DEBUG(dbgs() << "Deleting self-copy instruction: ");
|
||
|
|
LLVM_DEBUG(MI.dump());
|
||
|
|
InstrsToErase.push_back(&MI);
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
else if (MCID.getNumOperands() == 2 &&
|
||
|
|
MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
|
||
|
|
NumberOfSelfCopies++;
|
||
|
|
LLVM_DEBUG(dbgs() << "Deleting self-copy instruction: ");
|
||
|
|
LLVM_DEBUG(MI.dump());
|
||
|
|
InstrsToErase.push_back(&MI);
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
MachineInstr *DefMIToErase = nullptr;
|
||
|
|
if (TII->convertToImmediateForm(MI, &DefMIToErase)) {
|
||
|
|
Changed = true;
|
||
|
|
NumRRConvertedInPreEmit++;
|
||
|
|
LLVM_DEBUG(dbgs() << "Converted instruction to imm form: ");
|
||
|
|
LLVM_DEBUG(MI.dump());
|
||
|
|
if (DefMIToErase) {
|
||
|
|
InstrsToErase.push_back(DefMIToErase);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
if (TII->foldFrameOffset(MI)) {
|
||
|
|
Changed = true;
|
||
|
|
NumFrameOffFoldInPreEmit++;
|
||
|
|
LLVM_DEBUG(dbgs() << "Frame offset folding by using index form: ");
|
||
|
|
LLVM_DEBUG(MI.dump());
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// Eliminate conditional branch based on a constant CR bit by
|
||
|
|
// CRSET or CRUNSET. We eliminate the conditional branch or
|
||
|
|
// convert it into an unconditional branch. Also, if the CR bit
|
||
|
|
// is not used by other instructions, we eliminate CRSET as well.
|
||
|
|
auto I = MBB.getFirstInstrTerminator();
|
||
|
|
if (I == MBB.instr_end())
|
||
|
|
continue;
|
||
|
|
MachineInstr *Br = &*I;
|
||
|
|
if (Br->getOpcode() != PPC::BC && Br->getOpcode() != PPC::BCn)
|
||
|
|
continue;
|
||
|
|
MachineInstr *CRSetMI = nullptr;
|
||
|
|
Register CRBit = Br->getOperand(0).getReg();
|
||
|
|
unsigned CRReg = getCRFromCRBit(CRBit);
|
||
|
|
bool SeenUse = false;
|
||
|
|
MachineBasicBlock::reverse_iterator It = Br, Er = MBB.rend();
|
||
|
|
for (It++; It != Er; It++) {
|
||
|
|
if (It->modifiesRegister(CRBit, TRI)) {
|
||
|
|
if ((It->getOpcode() == PPC::CRUNSET ||
|
||
|
|
It->getOpcode() == PPC::CRSET) &&
|
||
|
|
It->getOperand(0).getReg() == CRBit)
|
||
|
|
CRSetMI = &*It;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
if (It->readsRegister(CRBit, TRI))
|
||
|
|
SeenUse = true;
|
||
|
|
}
|
||
|
|
if (!CRSetMI) continue;
|
||
|
|
|
||
|
|
unsigned CRSetOp = CRSetMI->getOpcode();
|
||
|
|
if ((Br->getOpcode() == PPC::BCn && CRSetOp == PPC::CRSET) ||
|
||
|
|
(Br->getOpcode() == PPC::BC && CRSetOp == PPC::CRUNSET)) {
|
||
|
|
// Remove this branch since it cannot be taken.
|
||
|
|
InstrsToErase.push_back(Br);
|
||
|
|
MBB.removeSuccessor(Br->getOperand(1).getMBB());
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
// This conditional branch is always taken. So, remove all branches
|
||
|
|
// and insert an unconditional branch to the destination of this.
|
||
|
|
MachineBasicBlock::iterator It = Br, Er = MBB.end();
|
||
|
|
for (; It != Er; It++) {
|
||
|
|
if (It->isDebugInstr()) continue;
|
||
|
|
assert(It->isTerminator() && "Non-terminator after a terminator");
|
||
|
|
InstrsToErase.push_back(&*It);
|
||
|
|
}
|
||
|
|
if (!MBB.isLayoutSuccessor(Br->getOperand(1).getMBB())) {
|
||
|
|
ArrayRef<MachineOperand> NoCond;
|
||
|
|
TII->insertBranch(MBB, Br->getOperand(1).getMBB(), nullptr,
|
||
|
|
NoCond, Br->getDebugLoc());
|
||
|
|
}
|
||
|
|
for (auto &Succ : MBB.successors())
|
||
|
|
if (Succ != Br->getOperand(1).getMBB()) {
|
||
|
|
MBB.removeSuccessor(Succ);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// If the CRBit is not used by another instruction, we can eliminate
|
||
|
|
// CRSET/CRUNSET instruction.
|
||
|
|
if (!SeenUse) {
|
||
|
|
// We need to check use of the CRBit in successors.
|
||
|
|
for (auto &SuccMBB : MBB.successors())
|
||
|
|
if (SuccMBB->isLiveIn(CRBit) || SuccMBB->isLiveIn(CRReg)) {
|
||
|
|
SeenUse = true;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
if (!SeenUse)
|
||
|
|
InstrsToErase.push_back(CRSetMI);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
for (MachineInstr *MI : InstrsToErase) {
|
||
|
|
LLVM_DEBUG(dbgs() << "PPC pre-emit peephole: erasing instruction: ");
|
||
|
|
LLVM_DEBUG(MI->dump());
|
||
|
|
MI->eraseFromParent();
|
||
|
|
NumRemovedInPreEmit++;
|
||
|
|
}
|
||
|
|
return Changed;
|
||
|
|
}
|
||
|
|
};
|
||
|
|
}
|
||
|
|
|
||
|
|
INITIALIZE_PASS(PPCPreEmitPeephole, DEBUG_TYPE, "PowerPC Pre-Emit Peephole",
|
||
|
|
false, false)
|
||
|
|
char PPCPreEmitPeephole::ID = 0;
|
||
|
|
|
||
|
|
FunctionPass *llvm::createPPCPreEmitPeepholePass() {
|
||
|
|
return new PPCPreEmitPeephole();
|
||
|
|
}
|