252 lines
8.2 KiB
C++
252 lines
8.2 KiB
C++
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//===-------------- BPFMIChecking.cpp - MI Checking Legality -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass performs checking to signal errors for certain illegal usages at
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// MachineInstruction layer. Specially, the result of XADD{32,64} insn should
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// not be used. The pass is done at the PreEmit pass right before the
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// machine code is emitted at which point the register liveness information
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// is still available.
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//
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//===----------------------------------------------------------------------===//
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#include "BPF.h"
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#include "BPFInstrInfo.h"
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#include "BPFTargetMachine.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "bpf-mi-checking"
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namespace {
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struct BPFMIPreEmitChecking : public MachineFunctionPass {
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static char ID;
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MachineFunction *MF;
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const TargetRegisterInfo *TRI;
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BPFMIPreEmitChecking() : MachineFunctionPass(ID) {
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initializeBPFMIPreEmitCheckingPass(*PassRegistry::getPassRegistry());
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}
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private:
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// Initialize class variables.
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void initialize(MachineFunction &MFParm);
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bool processAtomicInsts(void);
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public:
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// Main entry point for this pass.
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bool runOnMachineFunction(MachineFunction &MF) override {
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if (!skipFunction(MF.getFunction())) {
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initialize(MF);
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return processAtomicInsts();
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}
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return false;
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}
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};
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// Initialize class variables.
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void BPFMIPreEmitChecking::initialize(MachineFunction &MFParm) {
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MF = &MFParm;
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TRI = MF->getSubtarget<BPFSubtarget>().getRegisterInfo();
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LLVM_DEBUG(dbgs() << "*** BPF PreEmit checking pass ***\n\n");
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}
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// Make sure all Defs of XADD are dead, meaning any result of XADD insn is not
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// used.
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//
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// NOTE: BPF backend hasn't enabled sub-register liveness track, so when the
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// source and destination operands of XADD are GPR32, there is no sub-register
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// dead info. If we rely on the generic MachineInstr::allDefsAreDead, then we
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// will raise false alarm on GPR32 Def.
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//
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// To support GPR32 Def, ideally we could just enable sub-registr liveness track
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// on BPF backend, then allDefsAreDead could work on GPR32 Def. This requires
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// implementing TargetSubtargetInfo::enableSubRegLiveness on BPF.
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//
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// However, sub-register liveness tracking module inside LLVM is actually
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// designed for the situation where one register could be split into more than
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// one sub-registers for which case each sub-register could have their own
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// liveness and kill one of them doesn't kill others. So, tracking liveness for
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// each make sense.
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//
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// For BPF, each 64-bit register could only have one 32-bit sub-register. This
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// is exactly the case which LLVM think brings no benefits for doing
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// sub-register tracking, because the live range of sub-register must always
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// equal to its parent register, therefore liveness tracking is disabled even
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// the back-end has implemented enableSubRegLiveness. The detailed information
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// is at r232695:
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//
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// Author: Matthias Braun <matze@braunis.de>
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// Date: Thu Mar 19 00:21:58 2015 +0000
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// Do not track subregister liveness when it brings no benefits
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//
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// Hence, for BPF, we enhance MachineInstr::allDefsAreDead. Given the solo
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// sub-register always has the same liveness as its parent register, LLVM is
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// already attaching a implicit 64-bit register Def whenever the there is
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// a sub-register Def. The liveness of the implicit 64-bit Def is available.
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// For example, for "lock *(u32 *)(r0 + 4) += w9", the MachineOperand info could
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// be:
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//
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// $w9 = XADDW32 killed $r0, 4, $w9(tied-def 0),
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// implicit killed $r9, implicit-def dead $r9
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//
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// Even though w9 is not marked as Dead, the parent register r9 is marked as
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// Dead correctly, and it is safe to use such information or our purpose.
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static bool hasLiveDefs(const MachineInstr &MI, const TargetRegisterInfo *TRI) {
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const MCRegisterClass *GPR64RegClass =
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&BPFMCRegisterClasses[BPF::GPRRegClassID];
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std::vector<unsigned> GPR32LiveDefs;
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std::vector<unsigned> GPR64DeadDefs;
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for (const MachineOperand &MO : MI.operands()) {
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bool RegIsGPR64;
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if (!MO.isReg() || MO.isUse())
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continue;
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RegIsGPR64 = GPR64RegClass->contains(MO.getReg());
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if (!MO.isDead()) {
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// It is a GPR64 live Def, we are sure it is live. */
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if (RegIsGPR64)
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return true;
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// It is a GPR32 live Def, we are unsure whether it is really dead due to
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// no sub-register liveness tracking. Push it to vector for deferred
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// check.
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GPR32LiveDefs.push_back(MO.getReg());
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continue;
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}
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// Record any GPR64 dead Def as some unmarked GPR32 could be alias of its
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// low 32-bit.
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if (RegIsGPR64)
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GPR64DeadDefs.push_back(MO.getReg());
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}
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// No GPR32 live Def, safe to return false.
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if (GPR32LiveDefs.empty())
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return false;
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// No GPR64 dead Def, so all those GPR32 live Def can't have alias, therefore
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// must be truely live, safe to return true.
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if (GPR64DeadDefs.empty())
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return true;
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// Otherwise, return true if any aliased SuperReg of GPR32 is not dead.
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for (auto I : GPR32LiveDefs)
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for (MCSuperRegIterator SR(I, TRI); SR.isValid(); ++SR)
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if (!llvm::is_contained(GPR64DeadDefs, *SR))
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return true;
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return false;
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}
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bool BPFMIPreEmitChecking::processAtomicInsts(void) {
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for (MachineBasicBlock &MBB : *MF) {
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for (MachineInstr &MI : MBB) {
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if (MI.getOpcode() != BPF::XADDW &&
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MI.getOpcode() != BPF::XADDD &&
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MI.getOpcode() != BPF::XADDW32)
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continue;
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LLVM_DEBUG(MI.dump());
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if (hasLiveDefs(MI, TRI)) {
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DebugLoc Empty;
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const DebugLoc &DL = MI.getDebugLoc();
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if (DL != Empty)
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report_fatal_error("line " + std::to_string(DL.getLine()) +
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": Invalid usage of the XADD return value", false);
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else
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report_fatal_error("Invalid usage of the XADD return value", false);
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}
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}
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}
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// Check return values of atomic_fetch_and_{add,and,or,xor}.
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// If the return is not used, the atomic_fetch_and_<op> instruction
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// is replaced with atomic_<op> instruction.
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MachineInstr *ToErase = nullptr;
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bool Changed = false;
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const BPFInstrInfo *TII = MF->getSubtarget<BPFSubtarget>().getInstrInfo();
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for (MachineBasicBlock &MBB : *MF) {
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for (MachineInstr &MI : MBB) {
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if (ToErase) {
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ToErase->eraseFromParent();
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ToErase = nullptr;
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}
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if (MI.getOpcode() != BPF::XFADDW32 && MI.getOpcode() != BPF::XFADDD &&
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MI.getOpcode() != BPF::XFANDW32 && MI.getOpcode() != BPF::XFANDD &&
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MI.getOpcode() != BPF::XFXORW32 && MI.getOpcode() != BPF::XFXORD &&
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MI.getOpcode() != BPF::XFORW32 && MI.getOpcode() != BPF::XFORD)
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continue;
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if (hasLiveDefs(MI, TRI))
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continue;
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LLVM_DEBUG(dbgs() << "Transforming "; MI.dump());
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unsigned newOpcode;
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switch (MI.getOpcode()) {
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case BPF::XFADDW32:
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newOpcode = BPF::XADDW32;
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break;
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case BPF::XFADDD:
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newOpcode = BPF::XADDD;
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break;
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case BPF::XFANDW32:
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newOpcode = BPF::XANDW32;
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break;
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case BPF::XFANDD:
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newOpcode = BPF::XANDD;
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break;
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case BPF::XFXORW32:
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newOpcode = BPF::XXORW32;
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break;
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case BPF::XFXORD:
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newOpcode = BPF::XXORD;
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break;
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case BPF::XFORW32:
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newOpcode = BPF::XORW32;
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break;
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case BPF::XFORD:
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newOpcode = BPF::XORD;
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break;
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default:
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llvm_unreachable("Incorrect Atomic Instruction Opcode");
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}
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BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(newOpcode))
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.add(MI.getOperand(0))
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.add(MI.getOperand(1))
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.add(MI.getOperand(2))
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.add(MI.getOperand(3));
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ToErase = &MI;
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Changed = true;
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}
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}
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return Changed;
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}
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} // end default namespace
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INITIALIZE_PASS(BPFMIPreEmitChecking, "bpf-mi-pemit-checking",
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"BPF PreEmit Checking", false, false)
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char BPFMIPreEmitChecking::ID = 0;
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FunctionPass* llvm::createBPFMIPreEmitCheckingPass()
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{
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return new BPFMIPreEmitChecking();
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}
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